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Design >> RF Design >> spur - prediction from time domain
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Message started by cmos_cowboy on Jun 13^th, 2008, 3:56am

Title: spur - prediction from time domain
Post by cmos_cowboy on Jun 13^th, 2008, 3:56am

Hi,

I am designing PLL divider and I am trying to estimate spur levels based of deterministic jitter.
I have done some transient simulations with supply ripple and using veriloga code i can show the edge-to-edge period of the output.
How do I convert this data to phase noise?

thanks in advance,

cc

Title: Re: spur - prediction from time domain
Post by Ryan Cheung on Jun 14^th, 2008, 6:10am

Hi,

Do a fft on your transient waveform of Vc. Then convert the spectrum to VCO ouput by multiplying Kv/s. Then you will achieve the spur with the unit of dBc.

Title: Re: spur - prediction from time domain
Post by chenyan on Jun 14^th, 2008, 7:57am

Can you do a fft with time long enough?
I think you can see the spur tones but maybe not accurate enough amplitude

Title: Re: spur - prediction from time domain
Post by cmos_cowboy on Jun 16^th, 2008, 9:28am

Just to clarify. It is a digital type divider. All I am interested in doing at the moment is trying to work out the divider phase noise not the full PLL.
The divide values are large but the output is re-timed so I can reduce simulation time by reducing the divider value as only the front-end and sampler add jitter.
Hence the ouput frequency is higher that it would be in reality.
I can measure the edge-to-edge jitter of the ouput clock and plot it in the time domain.
However if say any periodic ripple is added to the supply, at a frequency that is not harmonically related to the output clock then this modulate the ouput and cause a spur.
I can take a pk-pk or rms of the Jee I record, this data is obviously periodic (at what will be the spur frequency) so only one period is required.
I dont think it is correct to try and convert this to phase noise in the ususual way (PN=20log(Jee_in_rads)) as it is not a gaussian distribution.
So how do I do it?