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Design Languages >> Verilog-AMS >> About the error " internal timestep is too small"
https://designers-guide.org/forum/YaBB.pl?num=1213783541

Message started by icsoul on Jun 18^th, 2008, 3:05am

Title: About the error " internal timestep is too small"
Post by icsoul on Jun 18^th, 2008, 3:05am

When measuring the frequency of a clock, I got the error information, " the internal timestep is too small".

My code is list in the following:

@(cross(V(clk)-vth, +1))begin
current_time = $realtime;
if (last_time > 0.0)
period = current_time - last_time;
freq = 1/period;
last_time = current_time;
end

V(pout) <+ period;
V(fout) <+ freq;

I think the problem comes from the statement, V(fout) <+ freq; .
Why it has no problem when using "V(pout) <+ period;", while it has the problem when using the statement "V(fout) <+ freq;"?

How to solve this?

Thanks !

Title: Re: About the error " internal timestep is too sma
Post by Stefan on Jun 18^th, 2008, 3:18am

The simulator tries to tighten the time steps until the convergence criteria abs[V(fout,t0)-V(fout,t0+delta T)] < epsilon is met.
Try normalizing your frequency output by a factor, that should help.

Title: Re: About the error " internal timestep is too sma
Post by icsoul on Jun 19^th, 2008, 2:18am

Stefan wrote on Jun 18^th, 2008, 3:18am:

The simulator tries to tighten the time steps until the convergence criteria abs[V(fout,t0)-V(fout,t0+delta T)] < epsilon is met.
Try normalizing your frequency output by a factor, that should help.

Thanks, Stefan.

Then how to normalize the frequency output?
I'm puzzled by this problem. the "V(pout) <+ period" works ok, while the "V(fout) <+ freq" does not work. I think they have the same quantity level. Why one works, but the other does not work?

Title: Re: About the error " internal timestep is too sma
Post by sheldon on Jun 19^th, 2008, 6:34pm

ICsoul,

For example for a PLL for Wireless LAN, normalize the frequency to GHz.
V(fout) <+ freq/1e9;

In general, having large ranges of numbers can cause simulators issues. Don't know
your application, but if the VCO has high kco then small variations, > 1mV, on the
control line cause big changes in the output frequency. On the other hand frequency
node may be a > 1GV.

Best Regards,

Sheldon

Title: Re: About the error " internal timestep is too sma
Post by icsoul on Jun 19^th, 2008, 10:43pm

sheldon wrote on Jun 19^th, 2008, 6:34pm:

Sheldon,

My application is to construct a pll model.

I had used the method you mentioned ever before. But the problem is still there.

The period has a quantity level 1E-9, it works ok. While the frequency has a quantity level 1E9, it does not work.

So there may be other reasons that cause this prolbem.

Title: Re: About the error " internal timestep is too sma
Post by Ken Kundert on Jun 19^th, 2008, 10:54pm

How big is V(fout)?
What is your supply voltage?

-Ken

Title: Re: About the error " internal timestep is too sma
Post by icsoul on Jun 22^nd, 2008, 4:58am

Ken Kundert wrote on Jun 19^th, 2008, 10:54pm:

How big is V(fout)?
What is your supply voltage?

-Ken

My supply voltage is 1.2V.
V(fout) is 0.279044V.
V(pout) is 3.5837V ( after x1E9 in the module), but this result is ritht.

Title: Re: About the error " internal timestep is too small"
Post by Ken Kundert on Jun 22^nd, 2008, 11:27am

The period is 3.5ns and the frequency is 0.279Hz?

Are you now normalizing the value of fout, or is the output voltage really 279MV?

What is fout driving? Do you need to connect the output frequency to the rest of your circuit, or do just want it available for plotting?

-Ken

Title: Re: About the error " internal timestep is too small"
Post by icsoul on Jun 23^rd, 2008, 5:04am

MY code:

`include "disciplines.vams"
`include "constants.vams"

module period_freq_meas (clk, pout, fout);

input clk;
output pout, fout;
electrical clk, pout, fout;

parameter real vhi = 1.2 ;
parameter real vlo = 0 ;
parameter real vth = (vhi+vlo)/2 ;

real last_time, current_time, period, px, freq;

analog begin
@(initial_step)begin
last_time = 0.0;
period = 0.0;
end

@(cross(V(clk)-vth, +1))begin
current_time = $realtime;
if (last_time > 0.0)
period = current_time - last_time;
px = period*1E9;
freq = 1/px;
last_time = current_time;
end

V(pout) <+ period*1E9;
V(fout) <+ freq;

@(final_step) begin
$strobe("freq = %g", 1/period) ;
$strobe("period = %g", period);
$strobe("fx = %g", 1/px);
$strobe("px = %g", px);
end
end
endmodule

And the stimulus:

X0 clk pout fout period_freq_meas
Vin clk 0 SFFM(0.6 0.6 2E8 5 2e7)

Please help to check it.

Thanks!~