The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> the preamp's noise impact on SARADC comparator &nb
https://designers-guide.org/forum/YaBB.pl?num=1213805348

Message started by SARdesign on Jun 18^th, 2008, 9:09am

Title: the preamp's noise impact on SARADC comparator &nb
Post by SARdesign on Jun 18^th, 2008, 9:09am

Hi designers:
I'm designing a high accuracy SAR ADC, so I have to consider the noise of the comparator whose architecture is preamp plus latch. In the cadence ADE we can plot the squared input and output noise, so should I integrate the output noise and extract root, then divide the DC gain, or integrate the input referred noise and extract root directly?
I prefer to the former, because when a small signal is amplified at the output, this output signal may be contaminated by the output noise then sampled by the latch, so, on this point, we should compare the output signal power with the output noise power. when I evaluate the SNR degradation of the preamp noise with matlab, I need the input referred noise power. it is right? but...
when I discuss it with the other colleague, he gives me the latter calculation method. his point is: the gain is change with the frequency.
can any body help me for a decision?

Title: Re: the preamp's noise impact on SARADC comparator &nb
Post by jerryzhao on Sep 2^nd, 2008, 11:43pm

I integrate the output noise and extract root, then divide the DC gain.and compare with 1/2LSB. Of course the gain is change with the frequency. But we only care the -3db bandwidth of preamp that gain almost same dc gain.

Title: Re: the preamp's noise impact on SARADC comparator &nb
Post by rf-design on Sep 22^nd, 2008, 3:45pm

You should be careful by estimating the equivalent input noise rms form AC noise simulations. The problem is that the noise contributions within the circuit are maximum at different times. Typical the AC noise estimation start with a circuit at a quite operating point. That work quite well for amps at stable DC operating points.

If you want to estimate the noise of the falling edge of an inverter there is only a very small contribution of the PMOS at these edge. If you bias the inverter so that the output is at the oberserving point the noise voltage is wrong by a factor.

Use the transient noise analysis.