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Design Languages >> Verilog-AMS >> how to realize a time-varying signal in verilog-a
https://designers-guide.org/forum/YaBB.pl?num=1214226139

Message started by wwm101 on Jun 23^rd, 2008, 6:02am

Title: how to realize a time-varying signal in verilog-a
Post by wwm101 on Jun 23^rd, 2008, 6:02am

i want to realize a time-varying sine signal which amplitude changes linearity with time，expression as vamp=k×t+vamp₀.where k is a coefficient and vamp₀ is an initial value。
how to realize it inverilog-a？
thank you in advanced！

Title: Re: how to realize a time-varying signal in verilog-a
Post by Stefan on Jun 23^rd, 2008, 6:50am

Check the Language reference manual.
This would do it
V(out) <+ k0*$abstime + V0;

Depending on your circuit you should also include a $bound_step .

Title: Re: how to realize a time-varying signal in verilog-a
Post by wwm101 on Jun 24^th, 2008, 6:03am

first ,thank you for your attention.
i realize in follow code：
//a timing-vary
`include "disciplines.vams"
`include "constants.vams"

module linamp(n1,n2);
electrical n1,n2;
real vamp;
parameter real freq = 1.25e9 from (0:inf);
parameter real k=100000 from (0:inf);
analog begin
vamp =k*$abstime;
V(n2,n1) <+ vamp * sin(2 * `M_PI * freq * $abstime);
end
endmodule