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https://designers-guide.org/forum/YaBB.pl Design >> RF Design >> optimum bias point https://designers-guide.org/forum/YaBB.pl?num=1214557367 Message started by aaron_do on Jun 27th, 2008, 2:02am |
Title: optimum bias point Post by aaron_do on Jun 27th, 2008, 2:02am Hi all, if you take a transistor is saturation, the gm is approximated as, 2IDS/(Vgs-VT) and in subthreshold it is approximately IDS/nVt For the input referred channel noise in the saturation region we have, Vn2=4kTγ/gm = 2kTγ(Vgs-VT)/IDS and in subthreshold, Vn2=2kTn/gm = 2kT(n2)Vt/IDS From these equations, it seems that subthreshold biasing offers better gm per IDS, better noise per IDS, and comparable noise per gm. Only drawback is subthreshold has higher input capacitance per gm (resulting in lower fT). Just want to double check if these manipulations seem strange to anyone? BTW i understand the difficulty in defining VT, however, i'm trying to confirm that weak-inversion (in between subthreshold and saturation) is basically the best biasing point. I also understand that linearity is poorer in weak-inversion/subthreshold... thanks, Aaron |
Title: Re: optimum bias point Post by vivkr on Jun 27th, 2008, 4:32am Hi Aaron, Yes, subthreshold biasing does offer higher gm/Id. In principle, this would be comparable to the gm/Id of a BJT except for the n factor below. All your deductions seem correct to me. I just dont know about the voltage noise expression you are using. If that is correct, then so is all else. Also, subthreshold operation entails a much greater sensitivity to mismatch and lower speed. Regards Vivek |
Title: Re: optimum bias point Post by didac on Jun 27th, 2008, 4:54am Hi, I agree with the deductions but I think that the effect of induced gate noise should be taken into account, I remember looking some papers about noise in high frequency transistors where the effect of induced gate noise in subthreshold caused a sharp increase in NFmin so I don't know if it holds the deduction about Noise. PD:I will try to search the reference about noise in subthreshold...it must be somewhere on my PC... |
Title: Re: optimum bias point Post by aaron_do on Jun 27th, 2008, 5:26am I got the noise expression for subthreshold noise from the MOS modeling book by Tsividis. I changed it around a bit though using the gm i wrote...it should be approximately correct. I'm very interested in that paper about the increase in NFmin in subthreshold if you can find it didac. Actually simulations do seem to show a sharp increase in noise somewhere around the threshold... thanks, Aaron |
Title: Re: optimum bias point Post by didac on Jun 27th, 2008, 5:45am Hi Aaron, I've found the following reference:http://ieeexplore.ieee.org/iel5/8611/27289/01213917.pdf, I remember finding similar conclusions on another more recent paper, let me see if I can find it. Hope it helps, |
Title: Re: optimum bias point Post by didac on Jun 27th, 2008, 5:51am Hi, The other reference links to the previous one, if you are interested is:http://ieeexplore.ieee.org/iel5/22/30324/01393200.pdf?tp=&isnumber=&arnumber=1393200, in the section IV, it's a paper focused on linearity and compares the noise due to the presence of a transistor in subthreshold making a composite transistor with another one in saturation. Hope it helps, |
Title: Re: optimum bias point Post by aaron_do on Jun 27th, 2008, 6:16am thanks, the second paper looks quite interesting anyway. I'll read it later. I read the first paper but there was something that didn't seem right. In page 2 column 1, paragraph 1, the author says that in the Van der Ziel Model, induced gate noise is inversely proportional to gm while the channel noise is proportional to gm. therefore gate noise will dominate when gm is low. however, gate noise is referred to the gate while channel noise is referred to the channel. If we refer both noise sources to the gate, then both are inversely proportional to gm so channel noise will still dominate. This makes more sense to me since the way i understand it, this gate noise is actually due to the equivalent resistance formed because the bottom plate of Cgs/Cgd is connected to the channel... Correct me if i'm wrong thanks, Aaron |
Title: Re: optimum bias point Post by didac on Jun 27th, 2008, 6:30am Hi, I need to think it more carefully so please don't kill me if I say something weird but I think that it's necessary an equivalent noise voltage generator and a equivalent noise current generator at the input(two-port noise theory) to take correctly into account the induced gate noise, the equivalent noise voltage generator only takes into account channel noise and the equivalent current generator takes into account both(channel and induced gate noise). PD:I will try to think a little bit more about this... |
Title: Re: optimum bias point Post by vivkr on Jun 27th, 2008, 7:06am aaron_do wrote on Jun 27th, 2008, 5:26am:
Hi Aaron, Tsividis is a reliable reference, but I am not sure about most simulation models. It would be good if you could find out how well the subthreshold region and noise are modelled in your process. Normally, good analog/RF processes have reliable models, but you never know. One good check would be to see if the Gm varies smoothly as you sweep the current down. You don't want to worry about "model noise". Regards Vivek |
Title: Re: optimum bias point Post by aaron_do on Jun 27th, 2008, 7:22am Hi, yes gm does transition smoothly. Its using BSIM3 model so technically NQS gate resistance isn't in the transistor model, but i believe it is modeled in the top level of the circuit model. didac, i've forgotten most of the two-port nosie theory and i usually just look at channel noise and equivalent noise voltage. But maybe your right. I also better think about it too.... cheers, Aaron |
Title: Re: optimum bias point Post by didac on Jun 28th, 2008, 2:25am Hi, I've checked the book "Design of Analog CMOS Integrated Circuits" by profesor Razavi and in the section of noise points that in presence of finite input impedance modelling the two-port with just a equivalent voltage noise source at the input it's incorrect(page 220) but I think that stills ignores contribution from induced gate noise(maybe I skipped something) in the book "The Design of CMOS RFIC" bt prof. LEE in the chapter of LNA design before the derivation of power constrain design method he derives the two-port representation of the MOSFET taking into account the induced gate noise. So I think that in the end is the old issue that up to which frequency(or situation) you can make some assumptions. PD:if you are interested just as historical curiosity I think that it could be interesting to see:"Theory of Noisy Fourpoles",H. ROTHEt, SENIOR MEMBER, IRE, AND W. DAHLKEt,Proceedings of the IRE,1956 |
Title: Re: optimum bias point Post by aaron_do on Jun 29th, 2008, 7:53pm Hi, just if anyone is interested, simulations seem to agree that noise per current is better with lower bias. Note however that i used an ideal voltage source at the gate rather than a port... cheers, Aaron |
Title: Re: optimum bias point Post by didac on Jul 1st, 2008, 2:25am Hi, Good to know, it's a shame that I can't simulate this things with my PDK.... Just as curiosity did you end up seeing something similar to the reference about noise(i.e a sharp increase in noise and then saturation of the noise)? Thanks, |
Title: Re: optimum bias point Post by aaron_do on Jul 1st, 2008, 5:05am Hi didac, i wasn't actually looking at the noise resistance or NFmin. I was simply looking at input-referred noise in V2/Hz. The IRN levels off below the threshold voltage as predicted. Strangely there is a sharp rise at around VGS = 0.6 V while the threshold is 0.48 V. However, the noise drops back down so that it is lower in the subthreshold region. I am going to try simulating this for more cases to double check. Maybe i'll post some results later... cheers, Aaron |
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