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Simulators >> RF Simulators >> IIP3 without PAC
https://designers-guide.org/forum/YaBB.pl?num=1214897800

Message started by aaron_do on Jul 1^st, 2008, 12:36am

Title: IIP3 without PAC
Post by aaron_do on Jul 1^st, 2008, 12:36am

Hi,

i've run into a problem where PAC and QPAC analysis don't work. Does anybody know a simple way to simulate IIP3 without using these two? I know it can be done with PSS alone but i think it would take ages to run with more than one input signal...

thanks,
Aaron

Title: Re: IIP3 without PAC
Post by pancho_hideboo on Jul 1^st, 2008, 1:34am

aaron_do wrote on Jul 1^st, 2008, 12:36am:

i've run into a problem where PAC and QPAC analysis don't work.

Why PSS/PAC and QPSS/QPAC don't work ?
Which do you invoke shooting or HB ?
How many tones do you apply as large signal ?

Title: Re: IIP3 without PAC
Post by aaron_do on Jul 1^st, 2008, 1:41am

Hi,

there were no errors, and the simulation completed normally, but the output was garbage...

For the simulation i basically just used the default settings. PSS was on shooting option. I don't know too much about the inner workings...

Basically I used a single transistor with common source configuration and check the drain current. PSS has a single tone at 1 MHz and PAC has a input at 1.1 MHz. I compared the PSS output at 1 MHz with the PAC output at 1.1 MHz and the difference was over 100 dB. Normally the difference is close to zero.

Anyway I think this is a PDK problem as i recently converted to a new PDK. I am currently talking to the foundry guys to see if they can solve it.

I've tried the exact same simulation in my old PDK and there were no problems. Both are 0.18 CMOS.

Title: Re: IIP3 without PAC
Post by pancho_hideboo on Jul 1^st, 2008, 1:51am

aaron_do wrote on Jul 1^st, 2008, 1:41am:

Anyway I think this is a PDK problem as i recently converted to a new PDK.

Are the any model descripted by Verilog-A in your PDK ?
For example, ESD diode, varactor, etc.

Often we face troubles in Verilog-A models when they are used in small signal analsys such as AC/SP, PAC.

Title: Re: IIP3 without PAC
Post by aaron_do on Jul 1^st, 2008, 1:54am

No, just a single transistor. Passive devices seem to be working fine so i guess there is some issue with the MOSFET model. However, its strange but other simulations seem to working fine: DC, AC, XF...

Aaron

Title: Re: IIP3 without PAC
Post by pancho_hideboo on Jul 1^st, 2008, 2:04am

aaron_do wrote on Jul 1^st, 2008, 1:54am:

No, just a single transistor.

In Current transistor model, model is composed of macromodel where intrinsic MOS and Verilog-A model sub block are combined.
Especially to express current dependent resistance and voltage dependent capacitance, etc., Verilog-A sub blocks are used.

So I think Verilog-A models are used in MOS model file.

Originally Verilog-A(AMS) is oriented to Transient Analysis.
So We have to take care of description scheme for small signal analysis.
Sometimes Verilog-A models can work in Transient Analsys but they give extraordinally results in small signal analysis. In this case we have to rewrite or reformulate Verilog-A model so that it can work for small signal analysis.

Title: Re: IIP3 without PAC
Post by Frank Wiedmann on Jul 1^st, 2008, 5:21am

This problem reminds me of a very similar one discussed at http://www.designers-guide.org/Forum/YaBB.pl?num=1204016124.

Title: Re: IIP3 without PAC
Post by aaron_do on Jul 1^st, 2008, 6:30am

Yes it does seem to be a similar problem. But unsolved... My circuit works for Pnoise analysis (including the transfer function plot in pnoise), but not PXF. Very strange...

I'll have a look tomorrow to see if the new PDK model is BSIM 3v3...

Aaron

Title: Re: IIP3 without PAC
Post by Ken Kundert on Jul 1^st, 2008, 10:23am

You could carefully check your setup. In particular, check pacmag and you sideband settings.

-Ken

Title: Re: IIP3 without PAC
Post by aaron_do on Jul 1^st, 2008, 6:45pm

Hi all,

thanks for all the suggestions. It turned out to be the same problem as the one Frank Wiedmann pointed to. The versions were different. (3.3 and 3.2). When i changed the version to 3.2, the output was correct. I will pass this info back to the foundry guys...

thanks again,
Aaron

Title: Re: IIP3 without PAC
Post by Frank Wiedmann on Jul 1^st, 2008, 11:15pm

You might also want to check with Cadence if they changed something in their BSIM3 model implementation from 3.2 to 3.3 that interferes with the small-signal PSS analyses.