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Simulators >> AMS Simulators >> VHDL-AMS cell in AMS-Designer - problem
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Message started by Pavel on Jul 2^nd, 2008, 5:34am

Title: VHDL-AMS cell in AMS-Designer - problem
Post by Pavel on Jul 2^nd, 2008, 5:34am

Hello,

Trying to "Design Prep" of very simple design that consisists of one cell - VHDL-AMS model of sinus generator, tool outputs error message:

"VHDL compile skipped for cellview LIB1.cell1:entity
because view name is 'entity"

View list: entity, schematic, symbol.

What this error means?

Best Regards.

Pavel.

Title: Re: VHDL-AMS cell in AMS-Designer - problem
Post by Stefan on Jul 2^nd, 2008, 5:40am

Did you include an architecture for your entity ?

Title: Re: VHDL-AMS cell in AMS-Designer - problem
Post by Pavel on Jul 2^nd, 2008, 6:00am

Thank you for answer Stefan.

I tried also with architecture

View list: entity, arch1, schematic, symbol

where arch1 - architecture view.

Nothing changed.