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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> One question on class-d audio design https://designers-guide.org/forum/YaBB.pl?num=1215151528 Message started by dandelion on Jul 3rd, 2008, 11:05pm |
Title: One question on class-d audio design Post by dandelion on Jul 3rd, 2008, 11:05pm Hi, I have a question on the class-d audio design. In the silicon test, I found the output will be shut down periodicly when the supply voltage is high or the input signal level is high. After FIB, I found the bounce of the digital VDD is high and it falsely triggered the auxiliary overheat protection block and then it output wrong alarm signal. So, output power stage is wrongly shutted down. What I am confused is, in the system simulations, the di/dt noise is simulated and the bording wire of package is also counted into the L*di/dt noise evaluations. But obviously, the bounce is larger than the simulation. I wonder why the big discrepancy between the simulation and actual silicon test results? Is there anything I missed in the designing? PLs. shed some light on it. Thanks a lot! |
Title: Re: One question on class-d audio design Post by ywguo on Jul 6th, 2008, 12:58am Hi dandelion, What do you hear when that class-D has such a fault? Yawei |
Title: Re: One question on class-d audio design Post by Visjnoe on Jul 6th, 2008, 9:52am Dear, 1. What value for the bondwire inductance did you use during simulations? 2. Have you run system simulations including all logic running from DVDD? 3. What was the rise time of any digital (switching) input you used during simulation? 4. Did you include a bondpad + package model in your simulations? Regards Peter |
Title: Re: One question on class-d audio design Post by dandelion on Jul 7th, 2008, 2:51am ywguo wrote on Jul 6th, 2008, 12:58am:
Hi yawei, The periodicly shutdown can be monitored in oscillope. The voice is not comfirtable. |
Title: Re: One question on class-d audio design Post by dandelion on Jul 7th, 2008, 2:57am Visjnoe wrote on Jul 6th, 2008, 9:52am:
I am thinking if it is the effect of the supply voltage pumping? I am not very clear this effect. Hope to get some comments from you. Thanks a lot |
Title: Re: One question on class-d audio design Post by Visjnoe on Jul 7th, 2008, 8:12am Dear, 1. What do you mean by supply voltage pumping? 2. 2nH seems a good value for the bondwire inductance. Would increasing it to 5nH let you replicate measurements? 3. Did you use an ideal voltage source for the supply in your simulations? Or did you use some finite impedance? Regards Peter |
Title: Re: One question on class-d audio design Post by dandelion on Jul 7th, 2008, 6:36pm Visjnoe wrote on Jul 7th, 2008, 8:12am:
Hi Oeter, Thanks for the help. 1.About the supply voltage pump, pls. refer the link http://www.diyaudio.com/forums/showthread/t-50861.html 2.Yes, I tried the 5nH inductance, but it seemed no much effect 3.Yes, I uesd the ideal supply voltage in my simulations. Maybe U should add some finite impedance for my system verifications. I wonder how do you describe the supply voltage in system simulations? Thanks a lot |
Title: Re: One question on class-d audio design Post by Visjnoe on Jul 7th, 2008, 11:55pm Dear, 1. If the DVDD is generated on-chip using a regulator, include this regulator in your simulation. This way, you will have a finite impedance (varying with frequency) instead of zero (ideal voltage source). 2. If DVDD is applied externally to your chip, you will at least have a bondwire towards your chip + bondpad parasitics + package parasitics. Maybe you already modelled the 'idea'l supply voltage this way. Other than (1) and (2) I don't have any suggestions at the moment. Regards Peter |
Title: Re: One question on class-d audio design Post by sck236 on Jul 9th, 2008, 7:47am dandelion wrote on Jul 7th, 2008, 6:36pm:
To see if it is supply voltage pumping, try to add a small resistor(10ohm) between the VDD and the ground. The reverse current will be sunken by the small resistor. Or you can add a huge capacitor between the VDD and the ground to minimize the rise in the VDD caused by the reverse current. Monitor the signal after the LC filter and the pumped VDD. If the VDD is pumped up when the signal is negative, it should be due to the reverse current. questions? Are you using a single ended load not BTL? Are you using the same regulator for the both of the digital VDD and the power stage? |
Title: Re: One question on class-d audio design Post by dandelion on Jul 9th, 2008, 10:05pm sck236 wrote on Jul 9th, 2008, 7:47am:
Thanks sck236 for the reply. It is helpful to me. I will try your proposal. We use the BTL instead of single ended. We have no regulator on the chip. The digital VDD/GND and analog VDD/GND is tied far at the pad, |
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