The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> AMS Simulators >> passing parameters in VHDL-AMS block
https://designers-guide.org/forum/YaBB.pl?num=1215602149

Message started by Pavel on Jul 9^th, 2008, 4:15am

Title: passing parameters in VHDL-AMS block
Post by Pavel on Jul 9^th, 2008, 4:15am

Hello,

How to pass timing parameter in VHDL-AMS block.
In my schema I use Clock generator and want to have a possibility
to rapidly change its frequency from schemati editor.

But VHDL time constants style "1 ms", "105 us", etc.
aren't properly interpreted by elaborator.

Elaboration pass and simulation runs, but clock period is some accidental value (very large by the way).

For example, clock period of following instatiation of clock oscillator is about 1.682 sec.

Help, please.

Code:

`include "disciplines.vams"
`include "constants.vams"

module CLOCK_GEN_test ( );

CLOCK_GEN #(.tclk("2 us")) (*
integer library_binding
= "LIB1";
*)
U_DUT ( .clk( clk ) );

endmodule