The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Measurements >> Phase Noise and Jitter Measurements >> Jitter and load capacitance
https://designers-guide.org/forum/YaBB.pl?num=1215682946

Message started by Visjnoe on Jul 10^th, 2008, 2:42am

Title: Jitter and load capacitance
Post by Visjnoe on Jul 10^th, 2008, 2:42am

Dear all,

I noticed a strange phenomenon during jitter simulation of driven circuits (in casu: logic gates). The simulator used was HSPICE RF.
The logic gates were driven by a 50% duty cycle square wave. The number of sidebands was set to 250 and the jitter integration bandwidth to 5GHz.

During a first set of simulations, I used a load capacitance of 0.1pF. I thought this was a conservative setting which would result in worst-case jitter results.

However, now I noticed that when I decrease the load capacitance to e.g. 0.01pF the reported jitter increases.

To me this is counterintuitive, since from handcalculations I would expect the jitter to decrease with decreasing load capacitance for synchronous (added) jitter by logic gates (e.g. INV, AND...).

Has anyone observed this too? Any (possible) physical explanation?

Regards

Peter

Title: Re: Jitter and load capacitance
Post by Ryan Cheung on Jul 13^th, 2008, 7:49pm

Hi,
I have found the same problem in eldoRF, but in spectreRF everthing seems reasonable. You could try the simulation in spectreRF.

Title: Re: Jitter and load capacitance
Post by trond on Aug 2^nd, 2008, 11:07am

Visjnoe wrote on Jul 10^th, 2008, 2:42am:

To me this is counterintuitive, since from handcalculations I would expect the jitter to decrease with decreasing load capacitance for synchronous (added) jitter by logic gates (e.g. INV, AND...).

Could you please point out a reference or link where I might be able to gain more mathematical insight into the jitter-load capacitance relationship.

Thanks

Title: Re: Jitter and load capacitance
Post by Visjnoe on Aug 25^th, 2008, 10:53am

Dear Trond,

please have a look at the paper by Abidi on jitter in ring oscillators. It contains several insightful derivations, including the jitter-load capacitance relationship. You can also derive the relationship yourself by reading the papers on jitter from this website.

Regards

Peter