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Design Languages >> Verilog-AMS >> Syntax Error when using spectre to simulation verilog-A file.
https://designers-guide.org/forum/YaBB.pl?num=1216548956

Message started by Julian18 on Jul 20^th, 2008, 3:15am

Title: Syntax Error when using spectre to simulation verilog-A file.
Post by Julian18 on Jul 20^th, 2008, 3:15am

Hi, there
I am very new to verilog-A field, so bear this simple question. I am runing Ken's sample and hold example and got the error like below:

Quote:

Error found by spectre during AHDL read-in.
"sh.va", line 5: "'<<--? include "discipline.h""
"sh.va", line 5: Error: syntax error
"sh.va", line 11: "electrical Pin,<<--? Nin, Pout, Nout;"
"sh.va", line 11: Error: syntax error

I am just using the spectre from command line(instead of simulating in ADE) and the command is

Quote:

spectre s_and_hold.scs

I wonder if I have to add some options in order for spectre to realize that the file contains verilog-A statements.

TIA.

Title: Re: Syntax Error when using spectre to simulation verilog-A file.
Post by Geoffrey_Coram on Jul 21^st, 2008, 8:57am

Did you
ahdl_include "sh.va"
in your .scs file? (Or were you using a regular include like for model files?)