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Modeling >> Behavioral Models >> behavioural modelling of a VCO for phase noise using Verilog -A
https://designers-guide.org/forum/YaBB.pl?num=1216630770

Message started by prem on Jul 21^st, 2008, 1:59am

Title: behavioural modelling of a VCO for phase noise using Verilog -A
Post by prem on Jul 21^st, 2008, 1:59am

Hi,
I am a new commer to he field of analog behavioural modeling.Presently i am trying to model a VCO that can give the phase noise..But i am really confused how to impliment this phase noise part.Is any body have the code for this please help me.....Thanks in advance.. :)

Title: Re: behavioural modelling of a VCO for phase noise using Verilog -A
Post by Stefan on Jul 21^st, 2008, 2:03am

Check the model section of this website.
Basically, you just randomly vary the period of the oscillator with a specific variance to reach the specified power level at the frequency offset.