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Design >> Analog Design >> about decap cell circuit
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Message started by mists on Jul 22^nd, 2008, 7:59am

Title: about decap cell circuit
Post by mists on Jul 22^nd, 2008, 7:59am

I see some standard cell library has decap cell? I want to know the circuit of this cell. just nmos or pmos transitor whose gate connect to one power rail and source-drain connect to the other power rail? does this scheme has ESD issue? thanks!

Title: Re: about decap cell circuit
Post by vivkr on Jul 22^nd, 2008, 11:28pm

This cell has no ESD issues. The only assumption is that there is some sort of global ESD clamp (central clamp) which will limit the difference between VDD-VSS to safe limits.

Vivek