The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> error when simulating Verilog-A model in ADE https://designers-guide.org/forum/YaBB.pl?num=1216739661 Message started by Pavel on Jul 22nd, 2008, 8:14am |
Title: error when simulating Verilog-A model in ADE Post by Pavel on Jul 22nd, 2008, 8:14am Hello, I just tested verilog-A model of nonlinear resistor that I have found in Cadence manual. Here i is. Code:
When I simulated following testbench (pls, see the picture), following error message appears in log window. Code:
What signifies this message? Thanks. Regards. Pavel. |
Title: Re: error when simulating Verilog-A model in ADE Post by Geoffrey_Coram on Jul 22nd, 2008, 12:49pm Works OK for me ... you might want to put "L,L" instead of "", though I think that's the default. |
Title: Re: error when simulating Verilog-A model in ADE Post by Pavel on Jul 22nd, 2008, 11:49pm Thanks Geoffrey. I tried your proposition. Here is the result: Code:
|
Title: Re: error when simulating Verilog-A model in ADE Post by Geoffrey_Coram on Jul 28th, 2008, 8:10am Hmm ... it may be that your simulator is too old a version. The $table_model in LRM 2.2 was donated by Cadence based on their implementation at the time, but it may be that it only supported file-based data, and the array data capability was added by the committee. |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |