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Design Languages >> Verilog-AMS >> Verilog-AMS equivalent to VHDL-AMS "ASSERT" and/or "REPORT"?
https://designers-guide.org/forum/YaBB.pl?num=1216789357

Message started by eemikej on Jul 22^nd, 2008, 10:02pm

Title: Verilog-AMS equivalent to VHDL-AMS "ASSERT" and/or "REPORT"?
Post by eemikej on Jul 22^nd, 2008, 10:02pm

I'm working on a Verilog-AMS model and want to use functionality similar to VHDL-AMS's ASSERT/REPORT capability to detect and report errors. As an example, I want to check for valid parameter values and report an error if needed (along with stopping design compilation/elaboration). Are there equivalent commands in Verilog-AMS? I know about the $display/$monitor/$strobe commands, but I can't see where any of these helps me with error detection (at least without some additional code) or, more importantly, stopping the compilation/elaboration process.

Thanks in advance...

Title: Re: Verilog-AMS equivalent to VHDL-AMS "ASSERT" and/or
Post by jbdavid on Jul 22^nd, 2008, 11:30pm

This part of the language has not been defined yet..
you'll have to roll your own until something standard gets defined..
'sok .. thats how PSL (aka sugar) got started too!..

Bob Peruzzi and I have documented a couple of different styles of the roll your own style in papers presented at the 2006(I think) BMAS ..
www.bmas-conf.org
(separate papers.. )

jbd