The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> S/H switches for pipelined ADC
https://designers-guide.org/forum/YaBB.pl?num=1216917790

Message started by HugoFranca on Jul 24^th, 2008, 9:43am

Title: S/H switches for pipelined ADC
Post by HugoFranca on Jul 24^th, 2008, 9:43am

I am designing a 10-bit pipelined ADC that will operate at 40MHz with a supply of 1.5V.

To calculate the maximum ON resistance of the switches I have:

1 - Calculated the maximum inclination of a full range (1V) sinusoidal input signal with 20MHz;

2 - Considered a static error to a ramp (with the inclination calculated before) of a RC system, smaller than 1/4 of LSB.

I got the maximum ON resistance of the switch to be 14.5 Ohms for a 500fF capacitor.

Since this resistance is very low I need switches of around W=140u and L=120n.

They look huge to me so I wonder what is your opinion.

If I use bootstrapped switches I can reduce then to half of the size.

Thanks for your help,

Hugo

Title: Re: S/H switches for pipelined ADC
Post by Berti on Jul 25^th, 2008, 3:46am

I think you did a mistake in your calculation.
From a rough estimation I think that Ron=1kΩ should
do the job.

Cheers

Title: Re: S/H switches for pipelined ADC
Post by loose-electron on Jul 28^th, 2008, 1:33pm

Why dont you put the sampling circuit together in a simulation and try it out? Do your switch sizing in the slow/weak corners for the MOS, and the 20% high corner for the capacitance value, to get the worst case RC time constant.

Title: Re: S/H switches for pipelined ADC
Post by ywguo on Jul 29^th, 2008, 2:31am

Hi Hugo,

That is a too tight specification. I am not clear your point. Would you please explain it?
Based on my understanding, that is not reasonable because it is not necessary for an S/H to capture very very fast in order to keep the error smaller than 1/4 LSB at any time. We just need it to settle within the specified error, say 1/4 LSB, at the end of the sampling phase.

Best regards,
Yawei

Title: Re: S/H switches for pipelined ADC
Post by HugoFranca on Jul 29^th, 2008, 6:29am

Thank you for the answers.

I think that my specifications was too tight and that I have now a clearer picture of the problem.

The switches and the sampling capacitor are equivalent to a low pass filter at the input of the ADC. If I calculate the Ron for a bandwidth of 100MHz (5 times the Nyquist freq.) I get a Ron of 636Ω.
This filter has very little influence in my 20MHz max. input freq in terms of gain, however it introduces a little phase (around 1 degree).
This little degree causes the input signal and the sampled signal to have a difference bigger than 1 LSB for the zero crossing points!
If I want this difference to be below 1/4LSB, the bandwidth of the sampling RC needs to be 4.4GHz, which corresponds to a Ron=14.5Ω!

So I think that I will ignore this small phase that is introduced and use switches with Ron of around 200Ω which are easy to do.

The circuit will NOT settle within, say 1/4LSB, at the end of the sampling phase, but I think that there is no big deal with this, right?

Cheers,
Hugo

Title: Re: S/H switches for pipelined ADC
Post by vivkr on Jul 30^th, 2008, 12:12am

HugoFranca wrote on Jul 29^th, 2008, 6:29am:

Thank you for the answers.

I think that my specifications was too tight and that I have now a clearer picture of the problem.

So I think that I will ignore this small phase that is introduced and use switches with Ron of around 200Ω which are easy to do.

The circuit will NOT settle within, say 1/4LSB, at the end of the sampling phase, but I think that there is no big deal with this, right?

Cheers,
Hugo

I am afraid that your understanding of the specs is still wrong. While the value of Ron you have chosen seems more reasonable, please bear in mind that an ADC is a sampling system, and switches are nonlinear blocks.

Unless your sampled signal settles to a sufficient accuracy within the sampling phase, you will get horrible distortion, and there is no point building a 10-bit ADC when the sampling switch is only 5-bit accurate.

If you don't believe me, just run a simple transient simulation of the switches and the cap, and look at the spectrum of the sampled signal.

There are 2 design challenges to resolve here, which depend on your application.

1. Settling accuracy for static signals. If there is already a sample-and-hold before your ADC (say), then your ADC will be digitizing static signals, more or less. So, you just need 2*Ron.C such that you have more than 7.7 time constants (for 66 dB settling accuracy) in the sample phase.

2. If you have a dynamic signal on the other hand, and this may be quite fast. You quote 20 MHz input, then the requirements are quite different. There is probably no hope to get good linearity, unless you bootstrap your switch. Because now, your switch timeconstants have to be so small that the switch tracks the changing input all the time. That is probably the reason why you got this 14.5 Ohm number. But with a bootstrapped switch, you will reduce the nonlinearity in the switch Ron, which will allow operation with a tolerable size switch (and a not so tolerable size for the bootstrap capacitor).

3. The nightmarish scenario if you are making a subsampled system, that is, your input signal still has a small bandwidth but the absolute frequency is very high. Then bootstrapped switches are the only way as well, but even they may have a hard time.

So, check if you have scenario 1 or 2 before you begin switch design, and do a transient analysis for distortion.

Regards
Vivek

Title: Re: S/H switches for pipelined ADC
Post by HugoFranca on Jul 30^th, 2008, 8:29am

Dear Vivek,

Thank you for your answer!

I am in the "case 2".
There is no separated S/H in my pipelined ADC, the S/H is done in the first multiplication stage, so the input signal can have a frequency up to 20MHz.

Now, one thing is the linearity of the switch and other is the maximum Ron value.

I was talking about the maximum value of Ron. And my conclusion is that for tracking the input signal within 1/4 LSB error, Ron should be bellow 14.5Ω which is very hard to get even with the bootstrapped switches. I don't see a solution for this and I couldn't find one in your answer.

The problem of the linearity, is another one. The total Ron (3 switches 1 passgate (250mV<Vin<750mV) and 2 NMOS (Vin=750mV) in series) varies between 108Ω and and 122Ω so this will cause some problems of linearity that I didn't measure yet but I think that this will not be the main issue.

Best regards,
Hugo

Title: Re: S/H switches for pipelined ADC
Post by HugoFranca on Jul 30^th, 2008, 8:55am

There was a small mistake with the voltages in my previous message so I will explain better.

The sampling is done with 3 switches in series.

One transmission gate connected between the input and the capacitor.The input signal can be between 250mV and 1250mV and Ron varies between 32Ω and 46Ω.

The 2nd and 3rd are simple NMOS connected in serie between the capacitor and VCM that is fixed to 750mV. Ron of each one is 38Ω.

So the total Ron changes with the input signal between 108Ω and 122Ω.

Hugo

Title: Re: S/H switches for pipelined ADC
Post by vivkr on Jul 30^th, 2008, 11:44pm

Hi Hugo,

You are right. My post did not give you any real suggestion. Here it is.

1. How accurately your sampled signal tracks your input signal is a spec assuming that you want
an absolute accuracy (offset+distortion) of around 11 bits from your S&H.

2. In reality, you do not need this tracking to be that accurate, if you can accept some offset and gain errors, and you have a switch whose Ron does not vary significantly with signal.

3. Still, I did a calculation assuming that you have to achieve 0.25 LSB tracking accuracy. In track mode, you have an equivalent Ron of all switches (I will call it Rtotal), in series with the sampling cap C. The tracking error = C(dV/dt)*Rtotal. For 0.25 LSB tracking error, you need Rtotal = 78 Ohms for C=0.5 pF, ADC fullscale=1V, and a 1 V sinewave at 20 MHz, and a 10 bit ADC assumed.
This is of course a very small value but would still not result in unit switches requiring 14.5 Ohm Ron. Still, this is impractical for such a small capacitor and such a moderate resolution ADC at this moderate sampling rate. So, ignore this.

4. If you were to make a bootstrapped NMOS switch and control the V(G.S) to be fairly signal-independent, you would have an Ron which would be more or less independent of Vin, leading to a fixed tracking error dV, which would be mostly benign, and some small distortion components. You may be able to use a larger Ron than what you would get from (3) above. In fact, ROn could be much larger, and you can decide how much signal loss you are willing to accept during the tracking phase.

5. If you use a simple transmission gate, you will need to ensure that the Ron is low enough that the variations in it do not cause a distortion larger than your target. Since Ron of a transmission gate is very nonlinear, you can assume that net error calculated in (3) is also the distortion error. So, if you wanted 0.25 LSB distortion from the sampling switch, make Rtotal < 78 Ohm.

One question: Why are you using 3 switches in series instead of 2? Are you doing time-interleaved pipelines with a 3rd master switch? 2 switches in series are bad enough. Also remember that tracking error results from every single switch when the input is a fast changing signal, and not just from the switch between the input and the cap. This should be obvious from the calculation I show in (3). Of course, the voltage levels and Ron variation are smaller for the other switches, but not negligible, as would be if the input were already sampled-and-held.

Regards
Vivek

Title: Re: S/H switches for pipelined ADC
Post by vivkr on Jul 30^th, 2008, 11:45pm

And one more thing. I would see if it were at all possible to change that VCM to an even lower value. The lower you can work with, the better for using NMOS switches alone to do the job.

Title: Re: S/H switches for pipelined ADC
Post by HugoFranca on Jul 31^st, 2008, 3:12am

Hi Vivek,

Thanks for your reply.
I have calculated again Rtotal using your formula and I got 15.5Ω.
I got 14.5Ω before because I was calculating with a 0.55pF capacitor.
Just to review the calculations I have:

Error = 1V / 512 /4 -- for 1/4 LSB between 1st and 2nd stage
dV/dt(max) = 0.5 sin (2Π * 20000000) = 2Π *10^7

Rtotal = (1/512/4)/(5*10^-13 * 2Π*10^7) = 15.5Ω

I need 3 switches because I using double sampling and the extra switch "syncronizes" the skew of each parallel sampling circuit.

To reduce the VCM is a good idea and I have tried that before but the problem is that it also changes the input CM of the OpAmp and I don't have time to optimize the OpAmp for the new CM because I will submit a prototype in September.
I have the ADC almost ready and I'm doing the layout in paralell with my simulations.

Cheers,
Hugo

Title: Re: S/H switches for pipelined ADC
Post by vivkr on Jul 31^st, 2008, 5:49am

HugoFranca wrote on Jul 31^st, 2008, 3:12am:

Hi Hugo,

1. A mistake in my calculation. I used 10x lower frequency. So if you were trying to get 0.25 LSB absolute error (@ 10 bit level), you would need 7.8 Ohms.

2. A mistake in your calculations. You are using a 9bit value as reference (512 instead of 1024). So, if you correct this, we both will get the same number ~ 7.75 Ohms or so.

3. I can imagine that it is a little difficult to change the CM level now. So stay with it. Double sampling was also obvious since you are using 3 switches. This is what I refer to as interleaved pipelines, since that's what they are also.

4. You should seriously try bootstrapping. It will be a lifesaver. But first try a simple transient simulation followed by an FFT to see how much distortion you are getting. For a good example of bootstrapping, refer to the JSSC paper by Dessouky & Kaiser, JSSC, Mar. 2001, Fig. 7 (if I remember). It is quite a large switch, mainly due to the bootstrap capacitance, but try to use it sparingly at the most critical places (all switches which are ON in the tracking phase would need it).
Once you have run such a simulation and seen where you are with respect to INL, you can decide what to do. There is no need to reduce absolute error if your switch is linear (bootstrapped).

5. Alternatively, try and see how far you get with just transmission gates. My guess would be that it would be just close enough for 10 bits.

6. The biggest question is also the INL you are willing to tolerate, because the sampling switch will only cause INL and no DNL in a standard sample-and-hold arrangement. For a 10bit ADC, I don't think you are willing to tolerate much INL.

Regards
Vivek

Title: Re: S/H switches for pipelined ADC
Post by ywguo on Aug 2^nd, 2008, 8:03am

Hi Hugo,

Please simulate the S/H and plot its FFT/fourier analysis result and calculate the THD.

If the settling error for a full scale step response is less than 0.5 LSB, I guess the THD/SNR is less than about 0.5LSB too. In other words, the S/H can achieve about 11 ENOB if the S/H settle to less than 0.5 LSB in the sampling phase, which converts to 7.6 times constants.

For a 40MS/s ADC, the sampling phase is often greater than 10ns. So the time constants should be less than 10ns/7.6=1.32ns. For a 0.5pF cap, the Rtotal = 263 Ω.

Best regards,
Yawei

Title: Re: S/H switches for pipelined ADC
Post by vivkr on Aug 4^th, 2008, 12:02am

ywguo wrote on Aug 2^nd, 2008, 8:03am:

Dear Yawei,

Your calculation implicitly assumes that the input signal is either a DC or is previously sampled-and-held by the preceding stage, because then the input is fixed, and the sampled value approaches it exponentially with a timeconstant given by the RC of the switch-capacitor network, which has the entire phase to settle.

However, Hugo is asking for settling accuracy when tracking a changing input. Here, the sampled output either needs to settle within 0.5 LSB or whatever accuracy level is desired in a much shorter time (if switch Ron is very nonlinear), or else the requirement is different if the switch Ron is almost linear. I think the calculations we both (Hugo and myself) show are correct, but not useful from a practical point of view since one either has to assume that all error that results is nonlinear and overdesign, or else, one assumes all error to be gain error (if switch Ron is 100% linear), and underdesigns a little using a bootstrapped switch.

Your point is perfectly correct that one needs to do an FFT of the transient output to see the THD.
This is the only way to really tell whether the required linearity is achieved or not.

Regards
Vivek

Title: Re: S/H switches for pipelined ADC
Post by Berti on Aug 5^th, 2008, 1:12am

Hi all,

Sorry, but to me this discussion is confusing. I have never seen nor measured a sampling circuit that needs a switch resistance as low as 15Ohms for the relaxed requirements of 40Ms/s and 10bit!

I fully agree with Yawei that 7.6 times the time-constant will do the job, and I don't
see why the sampled signal shouldn't track the input signal (since the RC time constant
is larger than the input signal frequency!)

Thanks for explanations!

Regards

Title: Re: S/H switches for pipelined ADC
Post by vivkr on Aug 5^th, 2008, 3:17am

Berti wrote on Aug 5^th, 2008, 1:12am:

Hi Berti,

Yes! the discussion has got a bit confusing. Let me try to clarify:

1. The 7.6 timeconstants allowance for the sampling phase implicitly assumes that the input is fixed for a 66 dB settling accuracy. This would happen if the input were already sampled-and-held.

2. Although the input signal is well within the bandwidth of the switch, the finite Ron combined with the current i(t) = C*dVin/dt will cause a drop dV = i(t)*Ron. Thus, there is a difference to (1). In (1), there is almost no current flowing into the switch at the end of the phase. However, the same is not true when you are applying a continuously varying input to the switch-capacitor-switch arrangement in track mode. There is always current flowing as the signal keeps on changing.

3. By itself, this drop dV would be harmless. If Ron were constant across all inputs of interest, you would have a gain error only => no nonlinear distortion. However, the Ron of a common transmission gate is highly nonlinear. The Ron may easily vary by a factor of 5-10 over input range.
So, one can assume that all error dV caused in this case is distortion, and must size Ron small enough to guarantee that the largest Ron gives small enough dV. Thus, one is forced to make the absolute error dV caused by the switch to be smaller than required nonlinear distortion spec. Hence the fantastically low Ron requirement. You could probably simulate and get an Ron spec about 2x times less tight, depending on the exact amount of nonlinearity from your switch, but you would still need a very large switch.

4. Now, if you have a relatively linear switch such as a bootstrapped switch, then you can assume that dRon across the input range is very small (< 10% of Ron). So the net error introduced by the switch has components dV = dVgain + dVnonlin, where the latter is about 10% of the total error. So you can use an Ron about 10 times or more larger, depending on your bootstrapped switch design.

I hope this makes the point clear. I cannot explain better. The best would be if you were to try to make a simple tracking circuit. You don't even need to turn the switches ON and OFF, just leave the tracking switches permanently ON and look at the voltage across the sampling cap, and take an FFT of this one for a rapidly varying input. Do this for the case where you have a common transmission gate, and for a bootstrapped switch (can be approximated with an NMOS whose gate-source voltage is fixed with an ideal voltage source). This is a very simple comparison but quite revealing.

Otherwise, ask people who have made sample-and-holds. This problem pops up there all the time. I came across it that way myself. The basic point I will emphasize again is that there is always a current flowing through the switch in the track phase when the input is changing all the time, and this is the main culprit.

Regards
Vivek

Title: Re: S/H switches for pipelined ADC
Post by Berti on Aug 5^th, 2008, 8:11am

Hi Vivek,

thank you, I got the point and understand you calculations now.
However, I think that the calculation doesn't make sense. One should do
a distortion analysis assuming that the switch is weakly nonlinear.
But Hugo never provided any information about the linearity of the switch (which of course will depend on the structure ... transmission gate, bootstraped etc).

I have already made sample-and-holds. That's why 15Ohm for 10bit@40MHz doesn't
sound reasonable to me (I more do 10bit@400MHz which would mean 1.5Ohm switch resistance ;).

Regards

Title: Re: S/H switches for pipelined ADC
Post by imd1 on Aug 5^th, 2008, 8:31am

It also seems too tight a spec to me.
The non-linear error is taken care of by bootstrapping the switch. There remains the non-linear capacitance, etc, so it's in your best interest to minimize the size of the switch to reduce that contribution w.r.t. the sampling capacitor (which should be *very* linear).

Now, this non-linearity consideration is already mixing some of the initial issues up.
Due to the RC constant of the switch there will always be a difference between the input signal and the voltage on the sampling capacitor.

Simple RC circuit behavior, phase error (so, time delay).

I don't see the point of trying to reduce that phase/delay error to less than one LSB, since the anti-aliasing filter at the input certainly contributes a lot more to this at the Nyquist frequency than what he seems to be designing for.

I usually get a spec for amplitude attenuation at nyquist, say -1dB, and implicitly I have there the phase error (or tracking error) that is acceptable.

Title: Re: S/H switches for pipelined ADC
Post by HugoFranca on Aug 5^th, 2008, 9:08am

Vivek,
I agree with your calculation, Rtotal should be less that 7.8Ω for a absolute error below 1/4LSB.

We all agree that this is not a reasonable value and so the ADC will introduce some phase error.
Thank you Imd1 for mentioning the effect of the anti-aliasing filter that will be dominating over the RC of the S/H.

Concerning the linearity of the switch:

Berti, in a previous post I have provided the information about the linearity of the switch.
For the moment I'm using 1 transmission gate in series with 2 NMOS. Within the input range Ron varies between 108Ω and 122Ω.

I agree that I should do the fft to see the effect of this non-linearity in the sampled signal, however I do not have time at the moment. (I have tried a few days ago but the result wasn't correct for some reason, and I couldn't conclude anything).
I will do the fft within a few months and I will post the results here, including the corners.

For now I just need to be sure that I'm not doing a big mistake in my circuit!

I have done a simple calculation to see the effect of the non-linearity of the switch using the expression provided by Vivek.
This is not a valid calculation because Ron=108Ω and Ron=122Ω do not occur at the same DC level and not even at the maximum dV/dt; however it gives an idea of the error.

Error @ 108Ω = 3.39 mV,
Error @ 122Ω = 3.83 mV

the difference is about 0.44mV which is relatively big when compared with 1 LSB that is about 1mV.

So if don't have time to do the boostrapped (I have done it but I need to update the clocking circuit and it takes time), I will at least try to reduce this non-linearity by decreasing Ron of the transmission gate switch (which will also improve the linearity).

Hugo

Title: Re: S/H switches for pipelined ADC
Post by HugoFranca on Aug 5^th, 2008, 10:38am

I have been playing with the L and W of the transistors of the transmission gate and I got to a point where the difference between Ron max and Ron min is around 3Ω.

Check the figure.

If I add to this the resistences of the 2 NMOS that are in series I get a Ron that varies between 106Ω and 109Ω.

Of course that this range is for a typical process, so it will get worse for the corners SF and FS.

But I think that for now I will not use bootstrapped switches.

Cheers,
Hugo

Title: Re: S/H switches for pipelined ADC
Post by vivkr on Aug 5^th, 2008, 11:55pm

Berti wrote on Aug 5^th, 2008, 8:11am:

Hi Berti,

Agree fully with you there. The structure of the transmission gate is crucial, and one ought to assume a weakly nonlinear switch, but if one is using a transmission gate, then this assumption is usually not valid. So, with a bootstrapped switch, it ought to be possible to get much more reasonable values for Ron (switch size), and good linearity.

As imd1 rightly points out, a larger switch will also introduce other nonlinear effects, and so it makes no sense to try and reduce Ron aggressively in an attempt to reduce absolute error, as this is neither useful from a system point of view, nor feasible or desirable.

Hugo:

I would still advise you to run atleast a simple transient simulation to see the distortion you are getting with your switch. From the Ron curves you posted, it would seem that you might be OK. However, there is no substitute for transient analysis. You mention that there was some problem with your transient analysis the last time you tried it.

Just try a simple simulation just of the sampling switches and the cap, with the clocking, and use coherent sampling and strobing for your simulation. Then, you can read out the data and do an FFT with sufficient clarity. In my experience, it takes < 10 minutes to set up everything and start a simulation, and the simulation itself should take 1 hour at the most. All in all, you can check everything in less than a morning's work.

On the other hand, if you find out that your circuit has too much distortion after the tapeout, then you can't do anything. Once the signal is ruined at the sample-and-hold, there is nothing to be done about it.

Think about it.

Regards
Vivek

Title: Re: S/H switches for pipelined ADC
Post by Monkeybad on Aug 6^th, 2008, 7:51pm

Hi! everyone!
I'm so glad that finally someone has discussed about the pipelined ADC.
I had designed a 30MHz pipelined ADC before. Some simulation experience may offer some help.
I agree with vivkr and Berti, in S&H simulation, the linearity simulation is needed. Calculation about the switch error just gives a roughly estimation about the performance. Using FFT test can show the real linearity that you can gain in S&H circuit. In my simulation experience , the bootstraped switches will need to get enough linearity in the spec of 40MHz, 10bit ADC.
Hope this provide some help!

Title: Re: S/H switches for pipelined ADC
Post by thomasross20 on Aug 8^th, 2008, 3:50am

Aha, good topic.
This may be wrong, but would be how I would approach it.

R = 1 / [2pi * 2f * C * 7.7]

Basically it has to settle within one clock pulse, not period, hence the 2f. 7.7 is because it will take 7.7 time constants to get to this value, so you have to divide by it. I believe C is the total capacitance, i.e. Cs + Cf, and R is the TOTAL resistance, so individual R's would have to be smaller.

But I believe the above is for a static input, from a S&H. I'm not following how you get Ron if no S&H is to be used....?

I have seen a few papers where either the S&H is not used, or it is left out completely and the time constants on both paths so that the MDAC and sub-ADC sample the same input rather than delayed versions. Personally, I am trying not to use a S&H and hope that the +-Vref/4 redundancy can compensate for any error. That, or use a very simple switch + cap, non-active S&H. I know a few folks have tried this, such as Ian Galton.