The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> modelling fractional delays in SIMULINK for continuous-time delta-sigma https://designers-guide.org/forum/YaBB.pl?num=1216987195 Message started by vivkr on Jul 25th, 2008, 4:59am |
Title: modelling fractional delays in SIMULINK for continuous-time delta-sigma Post by vivkr on Jul 25th, 2008, 4:59am Hi All, I am trying to model a fractional delay (0.5 sample) in my CT delta-sigma to account for the delay in the comparator, when making a SIMULINK model. The approach followed is similar to that in the paper by Mitteregger et al., JSSC, Dec. 2006. The CT blocks are modelled with a sample time of 0.01, the quantizer with sample time of 1, and the delay of the comparator = 0.5 samples, the DAC is modelled with a zero-order hold (ZOH) with sample time = 1. SIMULINK tells me to insert rate conversion blocks around the quantizer, and also between the quantizer and the comparator delay, and between the ZOH and the 0.5 sample delay. When I do this, I find that the rate conversion blocks behave as if they had a delay, which destabilizes my modulator entirely, as there is more delay than accounted for in the feedback path now. Is there a better way to model this? I am planning to build a model in Verilog-A now but the simulation speed with SIMULINK would be much higher, and so would be the ability to use various MATLAB features. Thanks Vivek |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |