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Design Languages >> Verilog-AMS >> How can I get real random number in Verilog-A?
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Message started by seefree on Jul 28^th, 2008, 10:21am

Title: How can I get real random number in Verilog-A?
Post by seefree on Jul 28^th, 2008, 10:21am

Hi,

I tried create a model with random value at each run, below is the code:

parameter integer seed = 2;
integer myseed, newseed;
real vrand;
analog begin
myseed=seed+$random();
newseed=seed*$random(myseed);
vrand = $rdist_normal( newseed, vmean, vsdev );
V(vp,vn) <+ vrand;
end
endmodule

I can run monte carlo analysis with different values, but same value for different runs, which makes it repeatable. In other words, when I re-run simulation, the value sequence from Random() function is the same. Can I create a model with the real random number? I tried to find a function in Verilog-A to get the system clock time to generize the rendom but couldn't find the function...

Thanks,

Title: Re: How can I get real random number in Verilog-A?
Post by icsoul on Aug 5^th, 2008, 4:32am

I don't think you can do that.

Becacuse any software including veriloga is based on some fixed algorithm. So there is no "real random".

Your original seed is fixed to 2, so the myseed and newseed are also in a fixed change mode.

If the seed is changed random or is deleted, the result may be better.

Good luck!~

Title: Re: How can I get real random number in Verilog-A?
Post by jbdavid on Aug 6^th, 2008, 9:44am

setup montecarlo to give you a random value of the seed parameter.