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Modeling >> Semiconductor Devices >> Long channel effects?
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Message started by Godfrey on Jul 29^th, 2008, 2:09pm

Title: Long channel effects?
Post by Godfrey on Jul 29^th, 2008, 2:09pm

I have a simple latch circuit (back to back inverters) buffering an analog input which is showing some odd behaviour on silicon. The feedback inverter is very weak and uses two long devices with W=2um and L=10um. The feedback inverter is only present to prevent leakage.

The circuit operates at low voltage (<1.5V) and from observations it seems that the feedback inverter is much stronger on silicon than shown when simulated.

Are there modelling errors due perhaps to some long channel effects for devices with very low W/L ratios?

Title: Re: Long channel effects?
Post by vivkr on Jul 29^th, 2008, 11:40pm

While the modelling of very narrow and long devices may not be quite accurate, I would be surprised if a 2/10 device is not modelled correctly. The W is not really minimum there. I assume you are not using a 2 um technology :) The aspect ratio is also not so bad.

If you want to get a good idea about the W, L values for which you have a good model, just look at your process doc. Usually, there are some notes about the transistor dimensions used in model parameter extraction. This is done for several different sizes, and the results are interpolated to arbitrary size devices.

Did you simulate your circuit across all reasonable corners and with the realistic input voltages?

Regards
Vivek

Title: Re: Long channel effects?
Post by Godfrey on Jul 30^th, 2008, 5:53am

I've resimulated it under all kinds of nasty conditions but the circuit behaves itself every time. The input waveform is a digital signal passed through an RC delay, so just a charging curve. I also checked the 'R' and also the 'C' models and saw no errors.

From silicon measurements, it looks like I have a factor of ~2 coming from somewhere. Maybe the Si has not been fab'd properly, I've checked the wafer test data once already, maybe I need another look.

Title: Re: Long channel effects?
Post by Godfrey on Jul 30^th, 2008, 8:24am

Theory #2 is that the latch inverter uses two transistors close to minimum size in the forward path and very long in the feedback path. So although this circuit simulates fine, on siicon, the two minimum transistors would be very susceptible to process variation and may be much weaker than expected (so the feedback inverter is overloading the output net).

Since the circuit is in the corner of the die, perhaps these very small transistors are badly registered.