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Design >> RF Design >> Does a lower VCO freq. produce more error in the FB divider o/p in a frac-N-PLL?
https://designers-guide.org/forum/YaBB.pl?num=1217862095

Message started by trond on Aug 4^th, 2008, 8:01am

Title: Does a lower VCO freq. produce more error in the FB divider o/p in a frac-N-PLL?
Post by trond on Aug 4^th, 2008, 8:01am

This has puzzled me a bit today.

Scenario 1)
Consider a fractional-N PLL. The VCO frequency goes into a chain of 2/3 dividers which are set by the sigma-delta modulator. The SDM works with a 16bit input word and produces a 3 bit output. Hence the divider divides by either N-3, N-2, N-1, N, N+1, N+2, N+3, N+4. The output will be approx. 26MHz.

Scenario 2) same as above, but the VCO frequency is divided by a fixed factor of two before going into the divider. The SDM has the same resolution, so the fractional part should be represented with the same accuracy. Only the N number is smaller now as we need to divide only by half as much.

Q) Will there be a difference in accuracy of the clock produced at the output of the divider?

From a mathematical point of view there should not be any difference as the SDM which produces the fractional part has the same accuracy.

However, intuitively, I could also argue that since the periods of the input to the FB divider are larger in scenario two, the FB divider will have less "resolution" in dividing it down (or matching to) to 26MHz.

Could anyone please share their thoughts on this topic.

Regards,

Ps. The divider used is from:

A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-m CMOS Technology

Title: Re: Does a lower VCO freq. produce more error in the FB divider o/p in a frac-N-PLL?
Post by zwtang on Aug 19^th, 2008, 9:37pm

The contribution to PLL phase noise from SDM quantization increases 6dB, because the timing resolution, the period of FB divider input, is double.

The Frequency Conrtrol Word should be shifted right one bit.
The other characteristics of PLL are the same.

Title: Re: Does a lower VCO freq. produce more error in the FB divider o/p in a frac-N-PLL?
Post by trond on Aug 20^th, 2008, 5:13am

Thanks for you comment Zwtang.

1)
Could you please further elaborate how you ended up with your conclusion? Please see my thoughts below.

2)
Also, I am not certain what you mean by shifting the control word to the right and what it would do.

--------------

I can see why you are saying we loose 6dB in the phase noise.
In the paper "A Dual-Mode Truly Modular Programmable Fractional Divider Based on a 1/1.5 Divider Cell" the authors derive an equation for the phase noise:

S_phi = 1/M^2 [fout_ave/f]^2 S_q(t).

Here M is the division ratio, fout_ave is the average frequency at the output of the divider, q(t) is the error from the SDM modulator which approximated the fractional part of the division with a bit-stream.

So by halving M I would increase the phase noise by 6dB.

What do you think about this explanations?

Thanks,

Title: Re: Does a lower VCO freq. produce more error in the FB divider o/p in a frac-N-PLL?
Post by zwtang on Aug 21^st, 2008, 6:09am

1) The input frequency of FB divider is halving, output frequency, 26Mhz, is maintained, so the divide-ratio (FCW) should be halved.

2) I agree with your explanations very well.
Please refer to the paper "A Quantization Noise Suppression Technique for ΔΣ Fractional-N Frequency Synthesizers", Nov. 2006, JSSC, the same authors.

Best Regards,
zwtang