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Simulators >> Circuit Simulators >> spectre error in transient sim.
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Message started by lrc on Aug 7^th, 2008, 9:41am

Title: spectre error in transient sim.
Post by lrc on Aug 7^th, 2008, 9:41am

Hi,

I am running a transient simulation using spectreVerilog, the simulation always stopped by the error below. Can anyone please tell me what might be the cause and how to avoid it?

Thanks very much.

Zhenning

Error found by spectre at time = 61.9654 us during transient analysis `tran'.
ERROR: Error in transient analysis IPC.
ERROR (SPECTRE-16328): Error in transient simulation for mixed-mode.

Analysis `tran' was terminated prematurely due to an error.
finalTimeOP: writing operating point information to rawfile.

Error found by spectre during DC analysis, during info `finalTimeOP'.
ERROR: Error in cleaning up IPC code in an attempt to quit.
ERROR (SPECTRE-16329): Error in DC simulation for mixed-mode.

Analysis `finalTimeOP' was terminated prematurely due to an error.

******************
DC Analysis `dcOp'
******************

Error found by spectre during DC analysis `dcOp'.
ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point.

Analysis `dcOp' was terminated prematurely due to an error.
dcOpInfo: writing operating point information to rawfile.

Error found by spectre during DC analysis, during info `dcOpInfo'.
ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point.

Title: Re: spectre error in transient sim.
Post by bharat on Jan 25^th, 2009, 8:20am

Did you get the answer to that?

Title: Re: spectre error in transient sim.
Post by Geoffrey_Coram on Jan 27^th, 2009, 11:18am

ERROR: Error in cleaning up IPC code in an attempt to quit.

sounds like something you should report to Cadence R&D.

Title: Re: spectre error in transient sim.
Post by Andrew Beckett on Jan 27^th, 2009, 12:53pm

This can happen (from a little research I did) when the verilog executable dies during the mixed-signal simulation. Spectre then reports it as seen above, because it can no longer talk to it.

I've found a few cases:

verilog ran out of memory
verilog wrote too big an output file
a system admin killed the process because it had been running a long time
licenses were released by verilog after a period of inactivity, and then couldn't be reclaimed later, and so verilog stopped.
use of some $wdf tasks to interface to the Synopsys Spice Explorer Tool
Path to some old version of verilog in the ADE->Digital Option setup.
Having a very old version of verilog in your path (use a recent IUS version)

There seemed to be lots of possible reasons - this was just a sample. I'd look in the verilog log file and see if that gives any clues...