The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> instantiating modules in Verilog-A blocks
https://designers-guide.org/forum/YaBB.pl?num=1218619858

Message started by Pavel on Aug 13^th, 2008, 2:30am

Title: instantiating modules in Verilog-A blocks
Post by Pavel on Aug 13^th, 2008, 2:30am

Hello

How to instantiate modules from other libraries in Verilog-A/Verilog-AMS blocks. For example, when I try to instantiate resistor block from analogLib library

Code:

res #(.Resistance(10k) R1(a,b);

compiler outputs error
line 20: Error: undeclared symbol res

Thanks in advance.

Regards.

Pavel.

Title: Re: instantiating modules in Verilog-A blocks
Post by Geoffrey_Coram on Aug 13^th, 2008, 6:25am

You should be able to instantiate a resistor with
resistor #(.r(10k)) R1(a, b);

as specified in Annex E of the Verilog-AMS LRM on Spice compatibility. However, I don't know how to instantiate cells from other libraries.

You might want to try generating a regular CDL netlist including analogLib cells and see how the netlister includes those blocks.

Title: Re: instantiating modules in Verilog-A blocks
Post by Pavel on Aug 13^th, 2008, 7:28am

Hello Geoffrey,

Thank you for response.
I tried your proposition.
CDL put in the top of netlist the description of block to be instantiated in form of subcircuit .SUBCKT.
For simple blocks it could be solution but for complex ones ...?

Thanks.

Regards.

Pavel.

Title: Re: instantiating modules in Verilog-A blocks
Post by jbdavid on Aug 13^th, 2008, 3:16pm

the difference between res and resistor is that res is a device in analogLib, that AMS has been setup NOT to support, while resistor is the spectre primitive that res actually uses too..

This is STILL an issue for simulator portability, one that could be solved by defining a nice library of basic primitives written in Verilog-A
(that could be mapped to standard spice or spectre primitives for those simulators without requiring anyone to change their models. )
and that would run in other simulators like GnuCAP
(ok.. I've STILL not actually run a recent version of that.. just no time for the experimentation)

as you no doubt realize there is not a 1:1 correspondence between spectre primitives and analogLib.. I suspect mainly because analogLib has to support many simulators.

jbd

Title: Re: instantiating modules in Verilog-A blocks
Post by Pavel on Aug 13^th, 2008, 11:50pm

Resistor case I presented only as example. Actually I would like to instantiate blocks from design kit libraries.
For example I wanted to create parametric Verilog-A cell that would contain a variable number of invertors (using generate statement). These invertors come from digital library of design kit. The purpose of such manipulation is to create a possibility to quickly change the number of invertors without recreating of a schematic.

But as I see in actual implementation it's impossible.

Thanks.

Regards.

Pavel.

Title: Re: instantiating modules in Verilog-A blocks
Post by jbdavid on Aug 27^th, 2008, 3:10pm

So Analog lib is specifically designed not to support AMS using its views since most of them call spectre primitives that are already supported..
for YOUR own library, if you are working inside CADENCE (ie icfb) for the veriloga, the cell you are instantiating SHOULD already exist in a library and have a symbol view.
then when you are done editing the veriloga, there is some parsing done to establish the link between the library you reference and the instances you include (this is the info inside the pc.db file in the CDB format..)
--
if you are working in a pure netlist environment, you just need to make sure that the element you instantiate can be found in one of
-Spectre builtin primitive
-model files included in the simulation setup
-a module defined in one of the verilog files included in the simulation.
--
Hopefully not more than one.. (ie don't make a resistor model called "resistor" !!!)
HTH
jbd