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Simulators >> Circuit Simulators >> How to simulate INL/DNL using spectre?
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Message started by thomasross20 on Aug 13^th, 2008, 3:24am

Title: How to simulate INL/DNL using spectre?
Post by thomasross20 on Aug 13^th, 2008, 3:24am

Hello,

I'm trying to find a way of simulating the INL/DNL of a fully-differential pipeline ADC in Cadence, using spectre/verilog-A. There is an ahdl library with DNL/INL blocks, but these are single-ended and their operation not explained well. Any help on this matter would be appreciated. Note the pipeline has a delay time before it starts outputting correct data..

Secondly, several references are at odds when defining the DNL of an ADC. Is it related to the width of the analog input along the x-axis or the height of the digital transition on the y-axis? I would say the analogue width...

Title: Re: How to simulate INL/DNL using spectre?
Post by ywguo on Aug 22^nd, 2008, 1:16am

Hi thomasross20,

The DNL/INL measurement cells are easy to use. Although their output are single-ended, it is not difficult to convert it to differential using ideal_balun in analogLib.

Another point is important and you have already noticed it. The pipelined ADC has a latency more than one clock cycle. That depends on the ADC arthitecture and stages. You often need modify the related Verilog-A code to record the right result. In the initial_step block in adc_dnl_8bit and adc_inl_8bit, they are tnext_high = tsettle/2; and tnext_low = tsettle. :)

Yawei

Title: Re: How to simulate INL/DNL using spectre?
Post by thomasross20 on Aug 22^nd, 2008, 4:07am

Thanks :)
I read the code a few times and it eventually made sense; I ended up writing my own version which drives the ADC with a differential input and non-overlapping clock, with an option to start the analysis after the initial delay :)
The only thing I'm having trouble with now is the CMFB for the gain-boosting amps; analogue design, don't you love it? :D