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Simulators >> Circuit Simulators >> Hit every code for DAC performance test such as SFDR
https://designers-guide.org/forum/YaBB.pl?num=1218691956

Message started by john_ana on Aug 13^th, 2008, 10:32pm

Title: Hit every code for DAC performance test such as SFDR
Post by john_ana on Aug 13^th, 2008, 10:32pm

Hi,

I am simulating a high speed 6b 3GS current DAC. For test such as SFDR, do we need to make sure that digital input hit every code?

For instance, I use a 3G clock and a 13/64*3G=609.375M input. I am using
64 point FFT to reduce the simulation time.
However, if I look at the input code histogram,
not all codes are hit since at the top and bottom
of the sine wave, some codes are repeated.

In order to hit all the codes, I have to use at
least 256 point FFT, which makes simulation
4 times longer since the simulation time is
Number_of_FFT*T_sample. This is only for
6-b DAC. In order to hit all codes for a bigger
DAC such as a 9-b DAC. the Number of FFT
points needed will be even larger.

Hence do we need to hit every code? or
we don't expect major difference if we
use 64 point FFT instead.

Thanks.

Title: Re: Hit every code for DAC performance test such as SFDR
Post by sheldon on Aug 14^th, 2008, 9:54pm

John,

My experience has been that you don't need to test all the codes to
estimate the dynamic performance, e.g., SFDR. However, there is
another phenomena you might want to consider. The noise floor of
the FFT is a function of the number of points in the FFT,
FFT Noise Floor is 10 log10 (M/2). See the link for more detailed
discussions,
http://www.analog.com/en/analog-to-digital-converters/ad-converters/products/tutorials/CU_tutorials_MT-001/resources/fca.html
I have actually found that for low-order data converters, 4-bit~6-bit,
sometimes you need to use more points for the FFT to get a clean result,
128~256 points.

Note:
This observation is just to accelerate simulation time, on the bench use as
many points as you like.

Best Regards,

Sheldon