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Design >> Analog Design >> improve LDO PSRR
https://designers-guide.org/forum/YaBB.pl?num=1219048592

Message started by trashbox on Aug 18^th, 2008, 1:36am

Title: improve LDO PSRR
Post by trashbox on Aug 18^th, 2008, 1:36am

Hi all guys,
I wanna design a high PSRR(-75dB) LDO (3.3v-->2.8v) with 3.3v device and the classic configuration is used: one stage nmos input pair error amplifier + a pmos (output stage).

However I found the PSRR at dc frequency is only -55dB. How to improve the PSRR performance? Thanks!

-- Trashbox

Title: Re: improve LDO PSRR
Post by Berti on Aug 18^th, 2008, 3:22am

I think that you basically need to improve the gain of your error amplifier.

Title: Re: improve LDO PSRR
Post by thechopper on Aug 18^th, 2008, 8:02am

Hi Trashbox,

Berti is right. Basically the PSRR of your LDO is proportional to the loop gain which, for your topology is set by the error amplifier gain.

This is specially true at low frequencies, where parasitic components do not play a significant role in the PSRR performance. Certainly at very high frequencies the story will be different.

Regards
Tosei

Title: Re: improve LDO PSRR
Post by trashbox on Aug 18^th, 2008, 8:19am

Hi thechopper and Berti,
Thanks for your advice. I read a paper by Dr. Rincón-Mora from Gatech and he proposed a PSRR model for LDO which has the same conclusion.

Title: Re: improve LDO PSRR
Post by spanandiyer1979 on Nov 3^rd, 2008, 7:59am

Hi Guys

Can you please take the time for answering my following queries regarding the LDO design:
1) I wanted a LDO design methodology for a low drop out regulator with an input voltage range of 2.8+/-10% , output voltage of 1.8V and a load current of 10mA to 50mA.i mean from the system specs , down to the amplifier specs etc.

2) How practical is it to design an LDO without an output capacitor.

thanks
anand