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Design >> Mixed-Signal Design >> How to model a CT ADC?
https://designers-guide.org/forum/YaBB.pl?num=1219110486

Message started by lightgo on Aug 18^th, 2008, 6:48pm

Title: How to model a CT ADC?
Post by lightgo on Aug 18^th, 2008, 6:48pm

Hi,
I am a beginner of ADC, my aim is to implement a 12-bits 10M signal width CT ADC. Now, i am focus on ADC modelling. Who can give me some suggestion or recommend something usefule? :)Thanks.

Title: Re: How to model a CT ADC?
Post by thomasross20 on Aug 19^th, 2008, 6:58am

There are two main options nowadays; these are to use a mathematics program such as matlab or scilab to do your modelling, or to use verilg-a/ams; this allows you to write your own analog modules using code, but the license costs can be hefty.

Title: Re: How to model a CT ADC?
Post by jbdavid on Aug 27^th, 2008, 1:37am

Most ADC's are pretty useless if they are not clocked..
usually when I see CT in conjunction with ADC, there is the also the term ΔΣ in front of ADC .. is this the case..
if so the CT time part is really an integration stage or two.
so a verilog-A model is quite possible.
so you need to model the Summing Amp (because you have to add the input with the FEEDBACK DAC) the FEEDBACK DAC, the integration, and the "SLICER" or internal FLASH ADC..
I recommend starting with that flash ADC and the DAC's first..
once you have cut your modeling teeth on those.. you'll be ready to try your hand at the integration stuff..

Title: Re: How to model a CT ADC?
Post by Paul on Sep 1^st, 2008, 1:09pm

If you have access to Matlab, you can get started with the discrete-time Delta Sigma Toolbox by Richard Schreier. This will give you a good starting point and improve your understanding of SD ADCs.

Regards,
Paul