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Design Languages >> Verilog-AMS >> verilog-A model for counter
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Message started by smarty on Aug 28^th, 2008, 7:36am

Title: verilog-A model for counter
Post by smarty on Aug 28^th, 2008, 7:36am

Hi all,
I am designing a temperature sensor and I would need to design a counter. But I wanted to test my design using behavioral model (verilog-A) model of counter.

I am not an expert in modelling. Can anybody help me out on this.

I need a counter which takes in serial input and converts it into a 8-bit parallel data.

Thanks and Regards,
SBR

Title: Re: verilog-A model for counter
Post by jbdavid on Aug 28^th, 2008, 11:36am

if you are using Cadence tools there are two libraries of interest shipped with the tools, ahdlLib, and bmslib.. there are examples of what you are looking for in there.
Also there are examples here on this site that may help you out.
jbd

Title: Re: verilog-A model for counter
Post by smarty on Aug 28^th, 2008, 8:19pm

Hi jbd,
Thanks.. I am working with cadence. i will look for the two libraries u mentioned and also search this site, if I get a little bit more info.

Best Regards,
SBR