The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Modeling >> Semiconductor Devices >> Strained Silicon
https://designers-guide.org/forum/YaBB.pl?num=1220119934

Message started by nano_RF on Aug 30^th, 2008, 11:12am

Title: Strained Silicon
Post by nano_RF on Aug 30^th, 2008, 11:12am

Hi All,

I am not sure if this is the right forum to post this. But nonetheless curious to know about following.

Lets assume that by process manipulation one has got a strained silicon device:-
(1) What could be the possible effect on devices deep-depletion breakdown? If it gets lower then why and vice-versa?
(2) This would be process dependent, but in general would one expect parasitics capacitance to increase?

Thanks in Advance,

Title: Re: Strained Silicon
Post by Berti on Sep 30^th, 2008, 7:40am

Hi,

The following paper probably answers your question:

C. Claeys et al., "Impact strain engineering on gate stack quality and reliability",
Solid-State Electronics (Pergamon Press), August 2008.

Regards