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Design >> Analog Design >> Flicker noise coefficient for a given technology
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Message started by Tareeq on Sep 4^th, 2008, 2:32am

Title: Flicker noise coefficient for a given technology
Post by Tareeq on Sep 4^th, 2008, 2:32am

Hi All,

[I am glad to write my first discussion on this forum, and I wish to all other members fruitful exchanges]

Imagine you'are a given a technology and you have to choose between Pmos or Nmos devices for the lowest generated flicker noise.

Furthermore, the power spectrum desnity of this noise if the form [K/(f.WL)].df where f is the frequency and K a constant and is the parameter of interest.

I would like to know how to set-up a testbench that would extract the coefficient K for both Pmos and Nmos.

Thanks !

NB: Althought generally speaking pmos generate less flicker noise, the spirit in this discussion is to have get this quantified.

Title: Re: Flicker noise coefficient for a given technology
Post by ywguo on Sep 4^th, 2008, 8:55pm

Hi Tareeq,

If the SPICE model for the given technology has modeled flicker noise, it is enough to extract the coefficient K using a common-source single-transistor configuration. I will run AC+noise simulation.

Yawei

Title: Re: Flicker noise coefficient for a given technology
Post by nano_RF on Sep 4^th, 2008, 8:55pm

Hi Tareeq,

The easiest way is to read through your process manual and read off flicker noise modeling parameter from therein. From there it will depend on whether its modeled BSIM or SPICE.

Just to get a feel of it you can do simple pnoise analysis using different device flavor and varying their aspect ratio. Then you can look at their flicker noise contribution.

Now whether PMOS is less noisier then NMOS totally depnds on the process technology. In some process PMOS is burried channel device and so less flicker noise contibutor (assuming gate interface defects was the main contributor). But you may have a process where PMOS and NMOS flicker noise is very much comparable.

Hope it helps.

Regards