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Design >> Analog Design >> bias decoupling capacitors
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Message started by modern_analog on Sep 6^th, 2008, 9:45pm

Title: bias decoupling capacitors
Post by modern_analog on Sep 6^th, 2008, 9:45pm

When you typically have a current mirror, people tend to put a cap on the gate line.

How does one decide how much cap to put there?

I have see only ad-hoc approaches but noone to give explanation on the optimum cap

Title: Re: bias decoupling capacitors
Post by pancho_hideboo on Sep 6^th, 2008, 11:41pm

modern_analog wrote on Sep 6^th, 2008, 9:45pm:

When you typically have a current mirror, people tend to put a cap on the gate line.
How does one decide how much cap to put there?
I have see only ad-hoc approaches but noone to give explanation on the optimum cap

It depends on input capacitance of gate, resistance of bias feed and operation frequency.

Title: Re: bias decoupling capacitors
Post by modern_analog on Sep 7^th, 2008, 5:37pm

Can you please be more specfic. Lets assume input gate cap is 1pF and bias resistance is 1ohm. Assume the frequency is 10G

Title: Re: bias decoupling capacitors
Post by thechopper on Sep 7^th, 2008, 5:55pm

I think pancho suggested that mainly depends up to which frequency you want the current mirror to work as such. By selecting the capacitor size in combination with the mirror RON you might get the desired -3dB frequency for the current mirror.

Regards
Tosei

Title: Re: bias decoupling capacitors
Post by hzfeiyun on Sep 11^th, 2008, 12:10am

modern_analog wrote on Sep 6^th, 2008, 9:45pm:

If for DC bias, it can be as large as possible.

btw, what is ad-hoc approaches?

Title: Re: bias decoupling capacitors
Post by ACWWong on Sep 11^th, 2008, 12:27am

hzfeiyun wrote on Sep 11^th, 2008, 12:10am:

btw, what is ad-hoc approaches?

ad hoc (http://en.wiktionary.org/wiki/ad_hoc) the usage in this case meaning impromptu i guess.

Anyway gate line filtering is very useful for bias noise filtering, as such R & C can be added and values chosen for a particular cut-off.

Title: Re: bias decoupling capacitors
Post by loose-electron on Sep 11^th, 2008, 10:31am

Agreed with above on this being a useful strategy. A couple of ideas here:

1. Figure out the minimal pole placement needed for the roll off point. Frequency of interest in a mixed signal system is generally the system clock and all of its harmonics.

2. Bias distribution over long distances, should NOT be done as a gate voltage. Convert the bias control to a current, pass the current across the chip, and then recreate the gate voltage locally in a diode connected transistor. This avoids ground noise modulation issues, and also avoid matching problems with widely seperated MOS devices.

3. When the bias current arrives at the local location, pass it thru an RC filter as it goes into the MOS diode. The LPF that you get there is working against a high impedance source (the remote current source) to get lower frequency pole (for the same C in the LPF) and the series resistance helps push the LPF pole lower in frequency for noise capacitively coupled into the wire in the long transit path across the chip.

4. That local filter capacitnace has a constraint of a minimum pole placement and size, but as you get into layout of the chip, if some spare space becomes avaialble, fill the available space with a bigger C. Can not hurt and might help.

5. As a general rule, I ***never*** send a chip out with white space in the layout. If its not filled with spare parts for metal mask fixes after the first tapeout, its filled with power supply decoupling or bias decoupling.

Not sold in stores!

:)

Jerry

Title: Re: bias decoupling capacitors
Post by hzfeiyun on Sep 11^th, 2008, 10:54pm

loose-electron wrote on Sep 11^th, 2008, 10:31am:

learn a lot, thanks

Title: Re: bias decoupling capacitors
Post by loose-electron on Sep 15^th, 2008, 8:31pm

not a problem, glad to be of help!

jerry

Title: Re: bias decoupling capacitors
Post by Berti on Sep 17^th, 2008, 1:33am

Just an other comment:

Current mirrors with low pole-frequency noise filters need more time for start-up. This might become a problem in certain applications (e.g. wireless transceivers), where
the chip has to be ready within a given time.

Cheers

Title: Re: bias decoupling capacitors
Post by ACWWong on Sep 17^th, 2008, 3:44am

Berti wrote on Sep 17^th, 2008, 1:33am:

yes thats a good point, startup and power down time needs design consideration/solution.