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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> bandgap trim and cap-less LDO issue https://designers-guide.org/forum/YaBB.pl?num=1220851599 Message started by trashbox on Sep 7th, 2008, 10:26pm |
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Title: bandgap trim and cap-less LDO issue Post by trashbox on Sep 7th, 2008, 10:26pm 1.how to realize the trim in bandgap? What's the difference between trim and options by logic control? 2.If LDO's dominant pole is at error amplifier's output and the phase margin is ok without large off-chip capacitor. Is it so-called cap-less LDO? In my design, use one-stage foled-cascode(get large output impedance at error ampifier out) and large pmos pass element (spec requires large output current) so that the pole at error amplifier is the dominant pole. Is it ok? Thanks! |
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Title: Re: bandgap trim and cap-less LDO issue Post by Tlaloc on Sep 9th, 2008, 8:04pm As far as the bandgap trim is concerned, the most common way that I have seen is to trim one of the resistors setting up the del-Vbe term in the equations. Of course, how accurate you need it is another question. If you trim with switches with binary weighted resistors, you can run the risk of the switch resistance interfering. If you can directly laser trim the resistors, you can get good results, but generally you can suffer from package shift. The only other way that I can think of with a voltage output is to change the transistor ratios, but this would be a very coarse trim. If you had a current output, you could also change the current mirror ratios. Again, that would most likely be pretty coarse. I did not understand what you second question in #1 meant. |
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Title: Re: bandgap trim and cap-less LDO issue Post by trashbox on Sep 10th, 2008, 12:31am Hi Tlaloc, Thanks for your comments. The second question in #1 means: If I use logic signal to control the resistor, means 2b'00 is 0.9*R, 2b'01 is R, 2b'11 is 1.1*R and 2b'11 is 1.2R to get a target bandgap output. Another question is, can trim techniques tune bandgap output even when there is process variation between different wafer? Suppose in mass production, bandgap from different wafer hasn't good output such as 1.1v, 1.2v, 1.3v, 1.2v etc. Can trim techniques tune all bandgap back to 1.2v around. How to realize it? Thanks! Tlaloc wrote on Sep 9th, 2008, 8:04pm:
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Title: Re: bandgap trim and cap-less LDO issue Post by Tlaloc on Sep 10th, 2008, 8:27pm Quote:
That is a type of trim, so I am still unclear what your question is. Quote:
None of the bandgaps that I have ever worked on ever had anywhere near that variation. If it did, it was broken. Quote:
In short, yes. Otherwise we wouldn't bandgap circuits in the first place since they wouldn't be manufacturable. Quote:
If my previous post didn't answer your question, what exactly would you like answered? |
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Title: Re: bandgap trim and cap-less LDO issue Post by hzfeiyun on Sep 10th, 2008, 11:55pm Quote:
None of the bandgaps that I have ever worked on ever had anywhere near that variation. If it did, it was broken. Is it possible for a general cmos process if they do not monitor VBE in wafer? Quote:
In short, yes. Otherwise we wouldn't bandgap circuits in the first place since they wouldn't be manufacturable. I guess you may need a auto-trimming method ? |
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Title: Re: bandgap trim and cap-less LDO issue Post by trashbox on Sep 12th, 2008, 2:37am Quote:
This type of trim is ok in lab test and I can set register by hand. However if mass chips are tested on ATE and the bandgap output need to be trimmed by this type. How does the equipment trim it automatically? I ever saw there are some extra pads in bandgap for trim. Can ATE trim the resistor in bandgap by these pads automatically? How does ATE works? Thanks! |
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Title: Re: bandgap trim and cap-less LDO issue Post by Tlaloc on Sep 12th, 2008, 9:40am You typically have some sort of OTP (one-time programmable) structure. These can be fuses, floating pmos, Non-Volatile Memory (Flash or EEPROM), etc. During test, the tester can determine the code, and then burns that code into the OTP. Then every time the part turns on, it reads it's own unique trim code back out of the OTP. |
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Title: Re: bandgap trim and cap-less LDO issue Post by trashbox on Sep 16th, 2008, 1:17am Hi Tlaloc! Thanks for your reference. It seems OTP has higher test cost. Right? Regards, Trashbox Tlaloc wrote on Sep 12th, 2008, 9:40am:
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Title: Re: bandgap trim and cap-less LDO issue Post by Tlaloc on Sep 16th, 2008, 7:53am It depends on the structure used. Fuses can have higher costs since they need a laser, but that is not generally true. Some of those mentioned can also be burned (written to) after packaging, so one could account for package stress as well. In some cases, depending on the flavor of OTP, they are not any more expensive. That is, they can be processed using a standard process, and they can be burned without special equipment. |
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Title: Re: bandgap trim and cap-less LDO issue Post by thechopper on Sep 18th, 2008, 7:01pm Tlaloc wrote on Sep 16th, 2008, 7:53am:
A typical example of these are polysilicon or just metal fuses. They are built out of regular components from standard process. Tosei |
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Title: Re: bandgap trim and cap-less LDO issue Post by msudans on Nov 20th, 2008, 10:56pm Hi trashbox, Regarding your Question2: Quote:
If your LDO does not have an external decap, it is a cap-less LDO. However, you may still need some internal decap to supply high frequency current spikes (typically 100-200pF). Once you add this internal decap, you will find that your uncompensated LDO phase margin is degraded and you will need miller compensation. Thanks, -m |
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