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Simulators >> AMS Simulators >> *E,NOTCMP problem.
https://designers-guide.org/forum/YaBB.pl?num=1220948095

Message started by holmes on Sep 9^th, 2008, 1:14am

Title: *E,NOTCMP problem.
Post by holmes on Sep 9^th, 2008, 1:14am

ncvlog: *E,NOTCMP:unit divder_mdl not found while parsing.

divder_mdl is a veriloga file.

it's ok in hierarchy editor.

how can i solve it?

thanks.

Title: Re: *E,NOTCMP problem.
Post by K.Riad on Sep 16^th, 2008, 10:34am

Hi Holmes,

Since your AMS compiles well in the HED mode, my first thought is your are defining some 'include directories' in HED and not in ADE.
If you are including verilog-A, then the compiler will look at this files in the 'include directory list'. I guess you have something defined in your HED mode : HED-> AMS -> Option -> Compiler -> Verilog-AMS -> Macros/Include -> Include Directory

If so, you need to include the same directories when working in ADE mode : ADE -> Simulation -> Options -> Compiler -> Include Path

Hope this helps.
Riad :-)

Title: Re: *E,NOTCMP problem.
Post by K.Riad on Sep 16^th, 2008, 10:43am

By The way, There is a usefull document in your cadence stream:
AMS in ADE Frequently Asked Questions:
$CDSHOME/doc/AMSinADEFAQ/AMSinADEFAQ.pdf

It's worth giving it a look ;-)

Cheers,
Riad.