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Design >> RF Design >> Negative Impedance seeing Vdd node of Inverters
https://designers-guide.org/forum/YaBB.pl?num=1221012939

Message started by pancho_hideboo on Sep 9^th, 2008, 7:15pm

Title: Negative Impedance seeing Vdd node of Inverters
Post by pancho_hideboo on Sep 9^th, 2008, 7:15pm

See attached figure.
This circuit is two cascaded inverters where these two inverters are biased as amplifier operation.

If load capacitance is relataive large, e.g. 10pF, an input impedance seeing a source of PMOS, that is connection terminal of vdd, shows negative impedance.

In attached figure, this impedance is evaluated as Zleft=Rleft+j*omega*Lleft.

If an impedance of vdd supply line is not enough small, this negative impedance causes oscillation at vdd supply line.

How to prevend this oscillation without lowering impedance of vdd supply line ?

Title: Re: Negative Impedance seeing Vdd node of Inverters
Post by nano_RF on Sep 11^th, 2008, 12:26pm

Hi,

First of all I personally did not like the biasing setup. Wouldn't it be good to have a DC bias that tracks with your supply. Lets say if VDD is increased then your sourcing ability is increased whereas sinking ability remain the same for the first stage. And for the second stage it is the Sinking that is increased whereas sourcing remain unchanged.

I would suggest to use a linearized inverter as the first stage. Basically connect a feedback resistor between input and output. that will set the DC bias pint for your first and second stage that will adjust itself with VDD change.

Just curious "what if you add another inverter, make it odd number stage". Does the negative impedance go away?

Regards

Title: Re: Negative Impedance seeing Vdd node of Inverters
Post by pancho_hideboo on Sep 11^th, 2008, 4:41pm

nano_RF wrote on Sep 11^th, 2008, 12:26pm:

I would suggest to use a linearized inverter as the first stage. Basically connect a feedback resistor between input and output.

Actually a self biased inverter with feedback resistor exists before this cascaded inverter.

nano_RF wrote on Sep 11^th, 2008, 12:26pm:

Just curious "what if you add another inverter, make it odd number stage". Does the negative impedance go away?

No, since gain of final this two cascaded inverter is large than other.

Title: Re: Negative Impedance seeing Vdd node of Inverters
Post by nano_RF on Sep 12^th, 2008, 9:51pm

pancho_hideboo wrote on Sep 11^th, 2008, 4:41pm:

Actually a self biased inverter with feedback resistor exists before this cascaded inverter.

So how does it look if you include the self biased inverter also in the simulation?

Title: Re: Negative Impedance seeing Vdd node of Inverters
Post by pancho_hideboo on Sep 12^th, 2008, 10:29pm

nano_RF wrote on Sep 12^th, 2008, 9:51pm:

So how does it look if you include the self biased inverter also in the simulation?

Of course there is negative impedance. Gate bias voltage of a figure I posted, 660.3mV, is an actual node voltage from total circuit.

Actually I noticed an oscillation of Vdd line in total circuits first when I ran a transient analysis with no signal input to inverters.
Total circuits are more more complex than "self-biased inverter" + "inverter" + "inverter".
Then I broke down and searched a cause of negative impedance in total circuits.
Finally I found out that final two cascaded inverters causes a negative impedance.

I understand the reason or mechanism why this two cascaded inverters cause negative impedance.

And depending on a impedance seeing Vdd node of inverters and a impedance seeing Vdd supply line or regulator output,
an oscillation could occur at Vdd node.

Again see a figure I posted, you can see "Impedance_Probe" inserted at Vdd node.
Zleft is an impedance seeing inverters and Zright is an impedance seeing Vdd power supply. In this case, Zright=0.
In actual total circuits, Zright is an impedance of Vdd supply or an output impedance of regulator.

These could be conditionally stable.
http://www.designers-guide.org/Forum/YaBB.pl?num=1218635777/0#5