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Design Languages >> Verilog-AMS >> Natural Log Convergence
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Message started by littlenasboy on Sep 11^th, 2008, 8:19am

Title: Natural Log Convergence
Post by littlenasboy on Sep 11^th, 2008, 8:19am

I'm working on a model which requires the use of the natural log operator. The model works fine when driven with voltage sources over the entire range of operation, but won't converge when using current sources.

Here is a sample of the code...

if (ID >=0) begin
LNID=ln(ID+1e-12);
end else begin
LNID=ln(ID+1e-12);
end

Perhaps the derivative blows up for ID values near 0...but I don't know how to prevent that...

Title: Re: Natural Log Convergence
Post by Geoffrey_Coram on Sep 12^th, 2008, 6:28am

I think you mistyped; the if and else blocks are the same.

You could have an issue, depending on the rest of your code, that the simulator uses an initial guess of 0 for the branch current. Then again, maybe not, since it's the same model code independent of what's driving.

You probably need to look more closely at your probes and sources (contributions). You might have something that looks like two current sources in series with a very slight mismatch in the sourced current. What if you put in a huge resistance in parallel, or shrink the 1e-12 so that it's less than abstol?