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Design >> RF Design >> low noise power amplifier?
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Message started by wizardyhnr on Sep 11^th, 2008, 8:57am

Title: low noise power amplifier?
Post by wizardyhnr on Sep 11^th, 2008, 8:57am

hi guys, i am now designing a LNA with specs of 0dBm input P1dB, 18dB power gain, and 1.5dB noise figure of 1710~1980 MHz.
I have several questions:
1. Is the LNA's behavior more like PA, 30 parallel bipolars to provide 60mA current. Should i take some simulation like PA to ensure its performance.
2. Is 0dBm input power level possible for SiGe HBTs, tran and pss+pac simulation results show the spec can be met, but i wonder whether the HBT can stand the input power level?
3. Would Darlington Structure show some advantage over simple common-emitter structure, Since at higher frequency, the parasitic inductance connected to bipolar emitter degrade the LNA's power gain dramatically.
i do appreciate if someone can help me!!!

Title: Re: low noise power amplifier?
Post by nano_RF on Sep 11^th, 2008, 1:09pm

Hi,

I would take LNA design totally separate entity wrt PA. You have different goals to achieve even though the basic matching network approach do not change.

I am not that much familiar with bipolar transistor. But I would guess that you should be able to handle 0 dBm of power that is roughly about .3 Volt peak in 50 Ohm system.

You should start out with a simple source/emitter degenerated, cascode structure. You can find this structure in any text book.

Regards

Title: ~
Post by wizardyhnr on Sep 12^th, 2008, 9:05am

First thank you for your advice. i have already tried simple common-emitter and cascode topology before. In fact, i do not think these specs are easy to met after simulation. for the cascode amp, the simulation results showed it's hard to achieve such a high linearity. For higher frequency such as 1710MHz, the emitter degeneration inductance would influence the Gmsg(Maximux power gain that can be achieved while the amp is stable) with a current of 50~60mA, in my design the relationship is
LE Gmsn
0.1nH 19.5dB
0.2nH 16.6dB
0.3nH 14.5dB
Some process may provide special ground metal panel beneath the substrate to minimize the bondwire inductance. Yet the process i am using does not provide this step, it's diffcult to control the bondwire inductance to such a low value. This is why i wonder is there any special circuit topology to meet the gain spec.
Anyway, thanks for your help!

Title: Re: low noise power amplifier?
Post by RFICDUDE on Sep 13^th, 2008, 7:28pm

Why do you need such a large bias current?
You may want to double check ft versus current density. If your devices are too small for the current then you could be operating beyond peak ft which would cause you problems with gain and process variation.

Title: Re: low noise power amplifier?
Post by wizardyhnr on Sep 15^th, 2008, 8:05am

a 0dBm input P1dB requires such a large current as i have mentioned. Besides, certainly only one transistor cannot stand such a current, so quite a number of transistors are in parallel to allow the current.

Title: Re: low noise power amplifier?
Post by nano_RF on Sep 15^th, 2008, 9:07am

wizardyhnr wrote on Sep 15^th, 2008, 8:05am:

Hey Wizardyhnr,

I guess I am not quite following you completely. First of all that inductive emitter degeneration get you to match to real impedance which should be the 50 Ohm. Secondly the degeneration helps you in the Linearity. Now cascoding helps you to isolate the input and output but most importantly it doesn't introduce extra noise given that your parasitic drain capacitance is not too much.

So, bottom-line is are you making sure that your input match is optimum when you have shown the realtion of degeneration inductance Vs Gain. Secondly this inductance will halso help you to get the linearity

Regards,
--Vikas