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Simulators >> AMS Simulators >> SpectreVerilog Voltage Level Problem
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Message started by bmwsky on Sep 15^th, 2008, 12:05am

Title: SpectreVerilog Voltage Level Problem
Post by bmwsky on Sep 15^th, 2008, 12:05am

Hi!

When I was using verilog function block to describe a digital cell and simulated it with analog part in spectre. I found that the output and input voltage level of the digital part is +5/0V, however, I'm designing circuits under 0.18um tech. So, my quesition is how to change the input and output voltage level of the digital block instead of the defualt +5/0V?

Thank you!

Title: Re: SpectreVerilog Voltage Level Problem
Post by ACWWong on Sep 15^th, 2008, 12:15am

You need to declare interface elements to get the levels correct. To do this with SpectreVerilog, I usually make a local copy of the analogLib cells MOS_d2a and MOS_a2d. Then under the mixed-signal drop down menu in the schematic you should be able to set the interface elements to apply by going ->interface elements-> library. Using this form you can edit your local MOS_a2d and MOS_d2a appropriately for your design (i.e. set the voltage levels and rise/fall times).
You can also set them as default or to a only apply to a particular cell.

good luck with it

cheers
aw

Title: Re: SpectreVerilog Voltage Level Problem
Post by Tlaloc on Sep 16^th, 2008, 8:05am

I have used that same approach without making copies of the IE. I use the defaults in analogLib but override their voltages in the same way. I generally parameterize the voltages, e.g. "vdd", so any sim that I (or any other designer) am running in the same library can use the parameterized name to handle arbitrary supply voltages. For the a2d elements, you could do something like "0.3*vdd" and "0.7*vdd" for those thresholds.

Title: Re: SpectreVerilog Voltage Level Problem
Post by ACWWong on Sep 17^th, 2008, 3:47am

Tlaloc wrote on Sep 16^th, 2008, 8:05am:

yes this approach is how it should work, but in the past i've found it rather temperamental as to whether the analogLib IE accepted the override... perhaps this issue has been solved within spectreVerilog since I last used it...