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Design >> RF Design >> MOSFET time constant...
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Message started by aaron_do on Sep 15^th, 2008, 5:14am

Title: MOSFET time constant...
Post by aaron_do on Sep 15^th, 2008, 5:14am

Hi all,

this might be a very simple question but anyway...just wondering what is the time it takes for a channel to form in a MOSFET? For example if we have a fixed V_DS and we apply a ramp to the gate from an ideal source, what would τ be in this expression...

I = V_DS/R_ON (1-e^(-t/τ))

thanks,
Aaron

Title: Re: MOSFET time constant...
Post by nano_RF on Sep 15^th, 2008, 9:47am

aaron_do wrote on Sep 15^th, 2008, 5:14am:

Hi Aaron,

Never really thought it in this way. I do see a problem in your formulation though. The RON is going to be Vgs or gate overdrive dependent. And i would think the time constant to be the product of the parasitic Cgs and the RON of the device. Does it makes sense?

Regards,
--Vikas

Title: Re: MOSFET time constant...
Post by loose-electron on Sep 15^th, 2008, 8:22pm

Aaron:

First order the resistance of the gates (distributed and awkward to define, but a first order guesstimate can be done) will be the resistance. The newer BSIM models (4.4 and later IIRC) has the Rgate in the model (although a LOT of foundries let it default to zero!) so in theory its in the model, but the value is not properly set most of the time.

The capacitance however is a bit different, it is nonlinear in nature due to the distributed depletion regions. (think PN junctions changing depletion regions) So here, you have Cgs, Cgd, Cgb as first order estimates. Not sure if the nonlinear nature of the capacitnace is in the model at all. Would have to go digging in the model details.

A suggestion: Most people do the layout of the transistors so that the Rgate is low enough (small widths for short gate stripes) to get the RC time constant small enough to not affect the performance.

That is not a definitive answer, but it is a way to get it out of the design problem.

Jerry

Title: Re: MOSFET time constant...
Post by vivkr on Sep 15^th, 2008, 11:07pm

Hi Aaron,

In addition to the points made by the others:

The charge in the channel is primarily sourced by the source/drain diffusion regions. As such, one would need to also account for the time it takes for the carriers to drift from the source and to spread out into the entire channel. This is relevant if you are dealing with extremely long channels. Otherwise, this effect should be negligible.

I am not sure but a foundry which accounts for NQS effects should be able to provide a model which automatically considers most of the effects responsible for the timeconstant you are talking about, certainly those related to gate resistance. Usually, any model intended for RF-CMOS should have the NQS feature enabled and modelled.

Regards,

Vivek

Title: Re: MOSFET time constant...
Post by aaron_do on Sep 17^th, 2008, 8:20pm

thanks for all the replies

I'm trying to think in terms of mixer design. For a down-conversion mixer, the output we're concerned with is at a much lower frequency than the switching. So i'm wondering if the main limitation on the switching is not the fT of the device, but the maximum speed at which the channel can switch. Does this seem reasonable?

thanks,
Aaron

BTW NQS gate resistance is approximately 1/5gdo right? So as a crude estimate, can we say (Cgs+Cgd)/5gd0 is the RC time constant? i.e. 3dB switching is approx. 5fT...