The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> pll's bandwidth and jitter
https://designers-guide.org/forum/YaBB.pl?num=1222308250

Message started by jimwest on Sep 24^th, 2008, 7:04pm

Title: pll's bandwidth and jitter
Post by jimwest on Sep 24^th, 2008, 7:04pm

Hi Folks,
I was puzzled when measuring the jitter of a integer-N PLL.
When the current of charge pump is increased, the jitter has been improved.
I was told the main cause of the jitter in an SoC should be the spur introduced by the power supply. In order to reduce the power noise, the minimum bandwidth should be achieved. The lower bandwith, the lower spur level is.
My question is why the larger bandwidth can improve the jitter performance?

Title: Re: pll's bandwidth and jitter
Post by Berti on Sep 25^th, 2008, 1:12am

Hmm, I don't think that interference in a SoC necessarily dominates the PLL jitter/phase noise. That depends on what dominates the phase noise of your PLL.
Maybe the VCO dominates the phase noise. In this case, larger bandwidth helps. I recommend you to take a look at the phase noise to identify the dominating component.

Cheers