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Design Languages >> Verilog-AMS >> How to introduce delay within conditional statement?
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Message started by vpen on Sep 26^th, 2008, 7:10am

Title: How to introduce delay within conditional statement?
Post by vpen on Sep 26^th, 2008, 7:10am

Hi everyone! please help. :'(... I want to introduce a delay within a conditonal if statement using Verilog-A.

My target code should function something like this:

if ( comp_flag == 1 )
I( VOUT, GND ) <+ transition( 0.0, rdelay);
else
V( VOUT, GND ) <+ transition( 0.0, fdelay);

but since its illegal to put transition() inside if conditons
i modified my code like below

I(iout) <+ transition( 0.0, rdelay);
V(vout) <+ transition( 0.0, fdelay);

if ( comp_flag == 1 )
I( VOUT, GND ) <+ I(iout) );
else
V( VOUT, GND ) <+ V(vout) );

The code has no error at compilation but the delay was not
accounted in the simulation?

What could be wrong with the code?

or

what alternative should i use? :'( :'( :'(

Title: Re: How to introduce delay within conditional statement?
Post by Geoffrey_Coram on Sep 26^th, 2008, 10:45am

In your modified version, are "vout" and "VOUT" distinct? Verilog-A is case-sensitive, but I'm not sure whether you were careful when excerpting your model.

I'd add two new nodes:
electrical int_iout, int_vout;
and contribute both like this:
I(int_iout) <+ V(int_iout) + transition( 0.0, rdelay);
I(int_vout) <+ V(int_vout) + transition( 0.0, fdelay);
then
if (comp_flag == 1)
I(VOUT, GND) <+ V(int_iout);
else
V(VOUT, GND) <+ V(int_vout);

The internal nodes have 1-Ohm resistors on them that convert the current into a voltage; there are funny tricks when you both contribute and probe I(iout) as in your code. In mine, the probe is always V(x).

Oh, and I assume the "0.0" first arg of transition() is just a dummy, you actually have something that changes there.