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Design >> RF Design >> How much mismatch percentage of the Charge Pump?
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Message started by email_gz on Oct 5^th, 2008, 11:57pm

Title: How much mismatch percentage of the Charge Pump?
Post by email_gz on Oct 5^th, 2008, 11:57pm

Hello All:
Does anyone know the value of how much mismatch percentage of the Charge Pump: |Iup-Idn|/Inormal in now days CMOS?
The value is better from the published paper, so I can use this
paper as an index.
Thank you very much!

Title: Re: How much mismatch percentage of the Charge Pump?
Post by rf-design on Oct 6^th, 2008, 2:19pm

You should consider static and dynamic mismatch.

The static mismatch get better by higher output impedance of the switched current sources. If you use a regulated switched current sources where the bias currents are regulated to follow the changing output voltage of the source, then smaller faster switches could be used. If you scale the Vdsat of the PMOS and the NMOS you can faily balance the switch on/off times. These remain relative stable also unter active bias control. The I guess you can about 2-5% static match and some 10ps dynamic mismatch.

Title: Re: How much mismatch percentage of the Charge Pump?
Post by loose-electron on Oct 9^th, 2008, 11:47am

The answer to this is going to be unique to your transistors and foundry selection. Suggest that you do a mismatch study from the statistical data on the foundry models, and look at that in conjunction wity your dynamic switching mismatch characteristics, and your dependence on output voltage variance effects on currents. They will all play in to the answer.

email_gz wrote on Oct 5^th, 2008, 11:57pm: