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Design Languages >> Verilog-AMS >> [Q] Verilog-A Modeling
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Message started by kidhyun on Oct 6^th, 2008, 5:25pm

Title: [Q] Verilog-A Modeling
Post by kidhyun on Oct 6^th, 2008, 5:25pm

Hi,

In a test bench for circuit, I added Verilog-A block which does only

> parameter real offset = 0;
> analog
> V(out) <+ V(in) + offset;

,where the offset is by default set to 0 in my simulation.
(I inserted this block in some place in the circuit)

I assumed that this block would not make any difference in the simulation result.

But when I checked the spectrum (using psd) there was significant difference between results with and without this block.

Just the existence of this block affect the time step in solving the node equations?

Thank You

Title: Re: [Q] Verilog-A Modeling
Post by jbdavid on Oct 6^th, 2008, 9:37pm

I'm going to go out on a limb here, and GUESS that by
"without" this circuit, you just had a wire ?

which would mean that you would have had a voltage, and, as needed current along that wire..

with this module you have, effectively an ideal VCVS with the control voltage being the input + offset..
Quite a different thing than

V(in,out) <+ offset;

which defines a branch between in, and out, with a fixed voltage (maybe 0) leaving its current unconstrained.. which will behave MUCH more like a wire..

HTH.

Title: Re: [Q] Verilog-A Modeling
Post by kidhyun on Oct 6^th, 2008, 11:51pm

Thank you. I think I made a mistake there. It works fine now.