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Design Languages >> Verilog-AMS >> Jacobian error in Cadence veriloga simulation
https://designers-guide.org/forum/YaBB.pl?num=1223461788

Message started by gandhi_gaurav on Oct 8^th, 2008, 3:29am

Title: Jacobian error in Cadence veriloga simulation
Post by gandhi_gaurav on Oct 8^th, 2008, 3:29am

I am trying to run a simple simulation to calculate the amount of charge that passes through a simple device and am getting a "jacobian" error.

The code that I am using is very simple as follows:

`include "constants.vams"
`include "disciplines.vams"

module res1(out,in);
inout out,in;
electrical out,in;
real i,charge,finalcur;

analog begin
i= I(out,in);
charge = idt(i);
finalcur = ddt(charge);
end
endmodule

The stimulus is a simple voltage source with 1mOhm resistance connected in series to voltage source. This is then applied to the veriloga block I have designed.

and the error that I am getting is zero found in diagonal of Jacobian.

Any guesses what am I doing wrong ?
How can I calculate the amount of charge that is passing through a device ?

Title: Re: Jacobian error in Cadence veriloga simulation
Post by Ken Kundert on Oct 9^th, 2008, 3:53pm

You need to specify an initial condition for the idt operator.

-Ken

Title: Re: Jacobian error in Cadence veriloga simulation
Post by gandhi_gaurav on Oct 31^st, 2008, 3:40am

Perfect !!

It works !!