|
The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> miller op amp compensation https://designers-guide.org/forum/YaBB.pl?num=1223628886 Message started by aaron_do on Oct 10th, 2008, 1:54am |
|
Title: miller op amp compensation Post by aaron_do on Oct 10th, 2008, 1:54am Hi all, very basic question here. I'm trying to design a miller op-amp, and i'm a bit stuck on the compensation. Question is, if i want to maximize the unity gain BW, am i right in saying i need to push the 1st non-dominant pole out as far as possible? That allows me to push the dominant pole out => wider bandwidth...Anyway in order to do this, I'm thinking I need to maximize the fT of the output buffer transistors. Does that sound right? Assume i'm driving a resistive load. thanks, Aaron |
|
Title: Re: miller op amp compensation Post by thechopper on Oct 10th, 2008, 2:37pm Hi Aaron, The GBW is set by the dominant pole location and obviously by the open loop gain. However the fist non-dominant pole will also set the unity gain frequency (fu), which will only be the same as the GBW if this second pole is at least at 5X higher frequency than the dominant one. So pushing out the first non-dominant pole helps get the fu closer to the GBW, which has a direct impact on the stability (in this case it improves it). So the real challenge is to move at higher frequencies the dominant pole with the same open loop gain (so GBW increases) without compromises too much the stability (which will be a function of the location of the second and higher order poles). As you suggested, to push the dominant pole to higher frequencies it is the ft that you have to maximize (in case your amplifier is a single ended one your frequency limitation might be related to the capacitance of a diode connected MOS when you convert to single-ended). Regards Tosei |
|
Title: Re: miller op amp compensation Post by raja.cedt on Oct 11th, 2008, 10:10pm hi Aaron, i have a basic question regarding this miller compensation. 1.dominant pole and open loop gain will set UGB(why 1st non-dominent pole at leat 5x from dominent ).Actually 1st dominet pole will decide phasemargin.correct me if am wrong 2.Does all the above discussion work for any load or only capacitor load. 3.can u provide any papers regading miller compensation failures(undersome conditions pole splitting wont work ) thank you. |
|
Title: Re: miller op amp compensation Post by thechopper on Oct 12th, 2008, 9:13am raja.cedt wrote on Oct 11th, 2008, 10:10pm:
Hi a 1-pole amplifier has a 90 degree phase margin (phase does not rotate more than 90 degrees). Adding a second pole (1st non-dominant pole) will set a smaller phase marging. According to the location of this second pole the phase margin will change. raja.cedt wrote on Oct 11th, 2008, 10:10pm:
Capacitor loads will bring secondary poles down to lower frequencies (compared with the resistive load only case). The discussion is general and regardless of what sets the location of the second pole (either the capacitor load - if exists - or a diode connected mos for example). Regards Tosei |
|
Title: Re: miller op amp compensation Post by aaron_do on Oct 12th, 2008, 6:47pm Hi tosei, I'm still a little skeptical. Quote:
It seems to me that if the non-dominant pole frequency is set, there is no way to increase the GBW of the dominant pole without compromising stability. The total phase shift at the non-dominant pole frequency is -135 degrees. So we must have fu less than the non-dominant pole frequency if we want phase margin > 45 degrees. If fu = non-dominant pole frequency, and we increase the pole frequency of the dominant pole, then the phase shift will exceed -135 degrees at fu. Miller compensation serves in part to reduce the dominant pole frequency by a large amount. So why would we need to increase the dominant pole frequency only to reduce it with miller compensation? Seems like the real challenge is to get the non-dominant pole frequency as high as possible. Since with miller compensation, the non-dominant pole frequency = gm/CL, we need to get the best fT for the second stage (Assuming resistive loads and CL is mainly determined by Cgd of the transistors). Please correct me if i've misunderstood something... thanks, Aaron btw, raja.cedt i'm not really sure about failure mechanisms...but as for loading, in addition to what tosei said, it seems to me that resistive loading would reduce the GBW of the amplifier if it is a standard miller op-amp. This is because if the non-dominant pole is higher than fu, and a resistive load is added, it will reduce the gain without increasing fu... |
|
Title: Re: miller op amp compensation Post by vivkr on Oct 12th, 2008, 11:31pm aaron_do wrote on Oct 10th, 2008, 1:54am:
Hi Aaron, The issue is slightly complicated. Normally, I too agree with you that one is better off with as few poles as possible for highest possible bandwidth. If you are using Miller compensation, then surely you are creating an additional pole where there was none before at Gm1/Cc, whereas you could have created a pole simply using the load capacitance using a single-stage scheme. I don't think I can answer your question directly, but a few points: 1. If you really must design a Miller compensated opamp in the first place, then Gray & Meyer tells me (4th edition, Chap. 9 on stability, Fig. 9.10) that gain-bandwidth is highest with a phase margin of 60 degrees. 2. Of course, the farther you push out the second pole, the farther you can also push out the first one. What counts is only the ratio of these 2, assuming you do not run into any other higher poles. But pushing the second pole out means burning more power in the second stage. Note that artificially forcing the first pole to be too low is usually not a good idea, since you lose bandwidth. So if you end up with the 2nd pole way out and a phase margin of 80 deg, that means: (a) You have chosen too large a miller cap or too small a Gm1 and could increase the bandwidth a bit (b) You are wasting too much power in the 2nd stage (Note that the 2nd stage typically consumes about 3x-4x power in classical Miller design). 3. I am sure you have accounted for this, but if you are worried about settling response more than steady-state response, then you are better off with as high a phase margin as possible. However, as you are driving resistive loads, this is obviously not the case. And for your case, you are right, you need to increase the bandwidth of your output stage (I would not use the term fT which has other implications as well). Regards, Vivek |
|
Title: Re: miller op amp compensation Post by aaron_do on Oct 12th, 2008, 11:55pm Hi Vivek, thanks. Only problem I have with your points is... Quote:
I don't have that book, but i'll try and get my hands on it. Anyway I think that you have to add the condition that there is no ringing in the step response. Otherwise i'm sure a phase margin of less than 60 degrees can achieve a higher GBW... btw you're right, fT is probably the wrong parameter to use. The main point i'm grappling with is am i right to think its better to have low over-drive in stage 1 for high gm/IDS, but higher overdrive in stage 2 for high gm/Cgd. cheers, Aaron |
|
Title: Re: miller op amp compensation Post by vivkr on Oct 13th, 2008, 2:25am Hi Aaron, You don't need the book by Gray & Meyer. You can check that the GBW is largest (without overshoot) with a phase margin of around 60 deg if you make a simple 2 pole opamp model with ideal elements in Cadence, and vary the second pole while keeping the first one fixed. Or you can analyze it by hand if you wish. You are right about settling without overshoot in my statement. I consider this kind of settling as good settling because the performance degradation in case of process variations or reduction in time available for settling is more graceful than in the case of ringing. As for your last point, I would put it a bit differently. Your Miller compensation will be degraded because of the capacitive divider formed by Cc and Cgs2. In other words, the effective Gm2 drops like this. So, you need to optimize the second stage between the 2 extremes of very high gm/Ids at the cost of very large Cgs2, and the other extreme of very small Cgs2 but very high current to achieve required Gm2 for stability. If you write out the simple equations accounting for the poles from stage1 and 2 and the cap divider (assuming the RHP zero is taken care of somehow), I am sure you can find out the optimal setting for gm/Ids so that you achieve stability and GBW at the lowest power. For the first stage, I would use high gm/Ids, but be careful not to increase your input cap excessively. Regards, Vivek |
|
Title: Re: miller op amp compensation Post by Tlaloc on Oct 13th, 2008, 7:45pm Quote:
Quote:
Now, I don't have my texts handy, so forgive me if my numbers are off. With that caveat, here is what I remember. 1) The step response settling time versus phase margin has a minimum at 53.6∘. The time increases sharply as phase margin continues to decrease. That is one of the reasons that people like 60∘ of phase margin since circuit variations will generally not cause the PM to decrease below 53.6∘. 2) A lot of people feel that 45∘ is sufficient for their designs, but it will have a slower settling due to ringing. This is more hazy, but I believe that 45∘ guarantees one (or two?) overshoots and one undershoot. 3) 60∘ guarantees maximum flatness in the frequency domain, but there most definitely is a mild overshoot in time. 4) The PM at which there is absolutely no overshoot in time is somewhere in the 70's, 72∘ or 73∘, I think. Adam |
|
Title: Re: miller op amp compensation Post by Frank Wiedmann on Oct 14th, 2008, 12:06am The phase margin for no overshoot is 76° (for a loop gain with only one dominant and one non-dominant pole and no zeros), see http://www.rdmiddlebrook.com/D_OA_Rules&Tools/Ch%2010.Basic%20Feedback.pdf, page 95. |
|
Title: Re: miller op amp compensation Post by raja.cedt on Oct 14th, 2008, 3:16am Hi, thanks all of you for giving answer.I understood pole splitting like the following Miller cap increase the load cap at the output of the 1st stage so that pole frequency decreases, at the same time output resistance of the 2nd stage will decreases so that pole frequency increases. Friends please correct me if any thing wrong. now the question is from the above discussion miller cap may lead to pole splitting(provided 1st stage output pole is dominant),or else poles may come towards each other provided(2nd stage pole is dominant). And another question is I saw "pole splitting considered harmful"(http://web.mit.edu/klund/www/papers/).i couldn't understand really in which way it is harmful,only thing it decreases the BW(but we dont have another alternative) Thanks, |
|
Title: Re: miller op amp compensation Post by Frank Wiedmann on Oct 14th, 2008, 5:48am Kent Lundberg quotes his paper "Pole splitting considered harmful" in http://web.mit.edu/klund/www/papers/ACC04_opcomp.pdf, saying: "While the above results are correct and useful, they are an impediment to intuition." He also says in this paper: "A pole-splitting approach to the compensation design is harmful to understanding. All of these techniques can be easily understood in a simple classical-control framework." |
|
Title: Re: miller op amp compensation Post by aaron_do on Oct 14th, 2008, 5:53am Hey raja.cedt, one thing about what you said though. Quote:
The way I understand it, output resistance does not reduce although you will see an increase in the output pole frequency. i.e. although for second stage, output pole is approximately gm2/CL, DC gain is still gm2Rout. This is something i'm still a little unsure about so correct me if i'm wrong. thanks, Aaron |
|
Title: Re: miller op amp compensation Post by thechopper on Oct 14th, 2008, 11:14am aaron_do wrote on Oct 14th, 2008, 5:53am:
Aaron, The ouput resistance will not change due to Miller effect, but output impedance will get reduced. Intuitively this can be observed by just considering that at higher frequencies, the miller cap will be a short. Under this condition, the 2nd output impedance will be 1/gm2 with Cin and Cout of this stage as the equivalent node capacitance. Regards Tosei |
|
Title: Re: miller op amp compensation Post by raja.cedt on Oct 14th, 2008, 9:50pm hi, in miller compensation output resistance reduces because there is capacitive feedback from out put to input makes output admittance gm*cc/(cc+cL1).where cL! is output resistance of 1st stage.so here r0 won't come into picture. Moreover its a shunt-shunt feedback so both o/p&i/p impedance will reduce through increase in cap at input and decreasing resistance at o/p. Can any body please send me POLE SPLITTING IS HARMFUL paper.i dont have access to download. thanks |
|
Title: Re: miller op amp compensation Post by aaron_do on Oct 14th, 2008, 11:36pm Hi raja.cedit, your equation gm*cc/(cc+cL1) is missing the output resistance of the first stage , r01. At low frequency, cc is open circuit, and because of r01, there is no feedback. So at DC, output resistance is r02, not 1/gm. Does that sound correct? It seems like some kind of black magic that you can get a pole at gm2CL without having the output resistance as 1/gm2... cheers, Aaron Aaron |
|
Title: Re: miller op amp compensation Post by vivkr on Oct 15th, 2008, 11:00pm Hi Aaron, At high frequencies (around the unity gain and higher), the Miller compensation cap is practically a short. Since this is connected between the gate and drain of the second stage driving transistor, you have a gate-drain short at high frequencies, and this "diode" offers resistance of gm2 to the output load cap CL for a second pole at gm2/CL. Of course, the real situation is slightly different since the Cgs of the second stage will change the action a little bit, but that's the basic idea. No black magic here, or anywhere else... Vivek |
|
Title: Re: miller op amp compensation Post by raja.cedt on Oct 15th, 2008, 11:44pm hi, i just want to know always miller compensation will give pole splitting or not(means this splitting depends on wether 1st stage , second stage has output dominant pole?) |
|
Title: Re: miller op amp compensation Post by vivkr on Oct 16th, 2008, 1:22am Hi, Pole splitting will occur only when the dominant pole is set by the compensation capacitance Cc. If you increase the value of this cap from zero to a certain optimum value, the dominant pole will rapidly move lower and lower, while the nondominant pole will move outwards. Beyond a certain point, increasing Cc will not cause the nondominant pole to move further or not much further. The second pole is set at Gm2/Cl. After this point, you need to increase Gm2 to move the second pole out. Note in particular that it is highly undesirable practice in general to go on increasing Cc, and Cc >= Cl will give diminishing returns. In a good design, Cc < Cl and preferably by a factor of 2-3. Otherwise, you are wasting power. In some exceptional cases (very low-bandwidth circuits), you may want to increase Cc a lot to reduce total inband noise. That's it. Vivek |
|
Title: Re: miller op amp compensation Post by aaron_do on Oct 16th, 2008, 6:02am Hi Vivek, I understand the part about the diode connection at high frequencies. What i don't get is this... At low frequency gain of second stage is gm2rout. Pole frequency is gm2/C because the resistance is 1/gm2. Since transconductance is gm2, gain at pole frequency should be approximately gm2/gm2. This is clearly not 3dB less than gm2rout. So where is the error? cheers, Aaron |
|
Title: Re: miller op amp compensation Post by vivkr on Oct 16th, 2008, 11:07pm aaron_do wrote on Oct 16th, 2008, 6:02am:
I don't understand your question? Why should the gain be 3 dB lower than the DC value? Are you saying that you expect the gain of the 2nd stage to be 3 dB lower than its DC value at the frequency where the 2nd pole is to be found? In that case, your analysis is slightly off track. The gain would have been 3 dB lower for the 2nd stage at the frequency corresponding the its pole were there no feedback (in form of the Miller cap) across this stage. That changes the dynamics. So, gm2/Cl is the 2nd pole of a Miller-compensated opamp, not the open-loop pole of the 2nd stage. That is something different, and in certain compensation schemes like the Ahuja scheme where there is no direct feedback across the 2nd stage, that situation is seen more clearly. I hope this answers your question. Regards, Vivek |
|
Title: Re: miller op amp compensation Post by aaron_do on Oct 17th, 2008, 5:04am Thanks. That basically answers my question. I like to simplify things as much as possible, and I was basically trying to compare the feedback case to an open loop case. Thanks for pointing out my error. I guess I know what i will be reading more about tomorrow... cheers, Aaron |
|
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |