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Design >> Mixed-Signal Design >> cycle stealing for implementing CDS etc. in delta-sigma ADCs
https://designers-guide.org/forum/YaBB.pl?num=1224137359

Message started by vivkr on Oct 15^th, 2008, 11:09pm

Title: cycle stealing for implementing CDS etc. in delta-sigma ADCs
Post by vivkr on Oct 15^th, 2008, 11:09pm

Hi All,

For really low-power delta-sigma design, one tries to use single-stage gain elements with gain around 30-40 dB instead of opamps and boost the gain with correlated double sampling (CDS) or correlated level shifting (CLS, ISSCC'08). The basic problem with both is the need for an extra phase where a coarse output is generated from which the finer one is then found. Note that mere offset cancellation does not need this extra phase in CDS, but gain improvement does. The gain typically goes up from A to A^2 for CDS.

Now it is a big sacrifice if one were to reduce the CLK rate to a lower level than the maximum possible CLK that one has available, because a reduction of the OSR even by factor 2 can increase the quantization noise considerably, or to put it the other way, if I use the full CLK speed, I can make a simpler modulator. So it is a must to use the maximum CLK possible.

I have heard of "cycle-stealing" schemes where the clock phases to the delta-sigma ADC are adjusted so that the effective CLK rate is still equal to the applied CLK but some phases are generated in between which allow use of CDS, usually based on the data pattern from the quantizer.

Could anyone tell me the basis for these cycle-stealing algorithms, or point out a reference?

Thanks,
Vivek