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Design Languages >> Verilog-AMS >> [q] how does verilog-A work in DC sweep?
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Message started by kidhyun on Oct 21^st, 2008, 2:08pm

Title: [q] how does verilog-A work in DC sweep?
Post by kidhyun on Oct 21^st, 2008, 2:08pm

Hi,

I have a question on the behavior of veriloga block in DC analysis. (DC sweep)

I have a veriloga block which looks like the following.

module X(in,out);
.....
real var1;

analog begin
@(initial_step)
var1 = 0;

....

My question is if I do DC analysis sweeping 'in' voltage from, let's say, 0 to 1V with the step size of 0.1V, is 'initial_step' block called every time when the simulator runs DC analysis (11 times)? or Is that 'initial_step' called only when 'in' voltage is 0V (only at the start point of DC sweep)?
(I only ran veriloga block with transient analysis, so I am a little bit confused.)

Thank You

Title: Re: [q] how does verilog-A work in DC sweep?
Post by solidstate on Oct 22^nd, 2008, 5:48am

I know that for e.g. an AC sweep over temperature, it processes the initial_step for every point of the sweep, so that should work for you too. Also, things like this are easily checked by adding something like $strobe("test") to the code that executes at an initial_step.

Title: Re: [q] how does verilog-A work in DC sweep?
Post by Geoffrey_Coram on Oct 22^nd, 2008, 6:49am

According to the Verilog-AMS Language Reference Manual, version 2.3,
@(initial_step)
only fires on the first step of a dc sweep; see Table 5-1 in Section 5.10.2, Global events.

This particular behavior was standardized in LRM 2.2; LRM 2.1 did not have a column for a dc sweep, so the behavior may not have been consistent in different simulators.