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Design Languages >> Verilog-AMS >> Verilog-A read bit_vector
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Message started by mitrobgenis on Oct 23^rd, 2008, 8:37am

Title: Verilog-A read bit_vector
Post by mitrobgenis on Oct 23^rd, 2008, 8:37am

I want to read a binary vector from a txt file or an integer or anything.
Each line has a 32-bit vector.
I use the following code. I want to read one line every clock cycle.
I read successfully one line but I do not manage to read the second line and so on.
I use the following code

analog begin
@(timer(0,period))
fid=$fopen("/home/cadence/dwa.txt","r");
$fscanf(fid,"%d",int_cs[1]);
V(cs) <+ transition(int_cs[1]);
end

Any ideas?

Title: Re: Verilog-A read bit_vector
Post by Geoffrey_Coram on Oct 23^rd, 2008, 12:38pm

Shouldn't you do the $fopen on @(initial_step) rather than every time the timer fires??

analog begin

@(initial_step)
fid=$fopen("/home/cadence/dwa.txt","r");

@(timer(0,period))
$fscanf(fid,"%d",int_cs[1]);

V(cs) <+ transition(int_cs[1]);

end

Title: Re: Verilog-A read bit_vector
Post by mitrobgenis on Oct 29^th, 2008, 2:10am

With the following code I manage to read the dwa.txt file with this format

1 0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1
0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0

`include "constants.vams"
`include "disciplines.vams"

module dwa_hdla(Mclk,cs0,cs1,cs2,cs3,cs4,cs5,cs6,cs7,cs8,cs9,cs10,cs11,cs12,cs13,cs14,cs15,cs16,cs17,cs18,cs19,cs20,cs21,cs22,cs23,cs24,cs25,cs26,cs27,cs28,cs29,cs30,cs31);

input Mclk;
output cs0,cs1,cs2,cs3,cs4,cs5,cs6,cs7,cs8,cs9,cs10,cs11,cs12,cs13,cs14,cs15;
output cs16,cs17,cs18,cs19,cs20,cs21,cs22,cs23,cs24,cs25,cs26,cs27,cs28,cs29,cs30,cs31;

electrical Mclk;
electrical cs0,cs1,cs2,cs3,cs4,cs5,cs6,cs7,cs8,cs9,cs10,cs11,cs12,cs13,cs14,cs15;
electrical cs16,cs17,cs18,cs19,cs20,cs21,cs22,cs23,cs24,cs25,cs26,cs27,cs28,cs29,cs30,cs31;

integer fid;
integer int_cs[31:0];

parameter real vtrans_clk = 1.65;
parameter real delay = 0;
parameter real rise_time = 1n;
parameter real fall_time = 1n;
parameter real period = 200n;

analog begin

@(initial_step)
fid=$fopen("/home/cadence/dwa.txt","r");

//@(timer(0,period))
@ (cross( V(Mclk) - vtrans_clk, +1 ))
begin

$fscanf(fid,"%d",int_cs[0]);
$fscanf(fid,"%d",int_cs[1]);
$fscanf(fid,"%d",int_cs[2]);
$fscanf(fid,"%d",int_cs[3]);
$fscanf(fid,"%d",int_cs[4]);
$fscanf(fid,"%d",int_cs[5]);
$fscanf(fid,"%d",int_cs[6]);
$fscanf(fid,"%d",int_cs[7]);
$fscanf(fid,"%d",int_cs[8]);
$fscanf(fid,"%d",int_cs[9]);
$fscanf(fid,"%d",int_cs[10]);
$fscanf(fid,"%d",int_cs[11]);
$fscanf(fid,"%d",int_cs[12]);
$fscanf(fid,"%d",int_cs[13]);
$fscanf(fid,"%d",int_cs[14]);
$fscanf(fid,"%d",int_cs[15]);
$fscanf(fid,"%d",int_cs[16]);
$fscanf(fid,"%d",int_cs[17]);
$fscanf(fid,"%d",int_cs[18]);
$fscanf(fid,"%d",int_cs[19]);
$fscanf(fid,"%d",int_cs[20]);
$fscanf(fid,"%d",int_cs[21]);
$fscanf(fid,"%d",int_cs[22]);
$fscanf(fid,"%d",int_cs[23]);
$fscanf(fid,"%d",int_cs[24]);
$fscanf(fid,"%d",int_cs[25]);
$fscanf(fid,"%d",int_cs[26]);
$fscanf(fid,"%d",int_cs[27]);
$fscanf(fid,"%d",int_cs[28]);
$fscanf(fid,"%d",int_cs[29]);
$fscanf(fid,"%d",int_cs[30]);
$fscanf(fid,"%d",int_cs[31]);

end
V(cs0) <+ 3.3*transition(int_cs[0]);
V(cs1) <+ 3.3*transition(int_cs[1]);
V(cs2) <+ 3.3*transition(int_cs[2]);
V(cs3) <+ 3.3*transition(int_cs[3]);
V(cs4) <+ 3.3*transition(int_cs[4]);
V(cs5) <+ 3.3*transition(int_cs[5]);
V(cs6) <+ 3.3*transition(int_cs[6]);
V(cs7) <+ 3.3*transition(int_cs[7]);
V(cs8) <+ 3.3*transition(int_cs[8]);
V(cs9) <+ 3.3*transition(int_cs[9]);
V(cs10) <+ 3.3*transition(int_cs[10]);
V(cs11) <+ 3.3*transition(int_cs[11]);
V(cs12) <+ 3.3*transition(int_cs[12]);
V(cs13) <+ 3.3*transition(int_cs[13]);
V(cs14) <+ 3.3*transition(int_cs[14]);
V(cs15) <+ 3.3*transition(int_cs[15]);
V(cs16) <+ 3.3*transition(int_cs[16]);
V(cs17) <+ 3.3*transition(int_cs[17]);
V(cs18) <+ 3.3*transition(int_cs[18]);
V(cs19) <+ 3.3*transition(int_cs[19]);
V(cs20) <+ 3.3*transition(int_cs[20]);
V(cs21) <+ 3.3*transition(int_cs[21]);
V(cs22) <+ 3.3*transition(int_cs[22]);
V(cs23) <+ 3.3*transition(int_cs[23]);
V(cs24) <+ 3.3*transition(int_cs[24]);
V(cs25) <+ 3.3*transition(int_cs[25]);
V(cs26) <+ 3.3*transition(int_cs[26]);
V(cs27) <+ 3.3*transition(int_cs[27]);
V(cs28) <+ 3.3*transition(int_cs[28]);
V(cs29) <+ 3.3*transition(int_cs[29]);
V(cs30) <+ 3.3*transition(int_cs[30]);
V(cs31) <+ 3.3*transition(int_cs[31]);
end

endmodule

Title: Re: Verilog-A read bit_vector
Post by mitrobgenis on Oct 29^th, 2008, 3:09am

A little bit better....

// VerilogA for dmitrovgenis_lib, dwa_hdla, veriloga

`include "constants.vams"
`include "disciplines.vams"

module dwa_hdla(Mclk,cs);

input Mclk;
output [31:0] cs;

electrical Mclk;
electrical [31:0] cs;

integer fid;
integer int_cs[31:0];
integer j;

parameter real vtrans_clk = 1.65;
parameter real delay = 0;
parameter real rise_time = 1n;
parameter real fall_time = 1n;
parameter real period = 200n;

analog begin

@(initial_step)
fid=$fopen("/home/cadence/dwa.txt","r");

@ (cross( V(Mclk) - vtrans_clk, +1 ))
begin
for (j=0;j<32;j=j+1)
begin
$fscanf(fid,"%d",int_cs[j]);
end
end

generate i (31,0) begin
V(cs[i]) <+ 3.3*transition(int_cs[i]);
end

end

endmodule

Title: Re: Verilog-A read bit_vector
Post by jbdavid on Oct 29^th, 2008, 10:02am

that second version does look a lot better..