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Design >> RF Design >> frequency divider operating range
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Message started by jlee on Oct 27^th, 2008, 8:02pm

Title: frequency divider operating range
Post by jlee on Oct 27^th, 2008, 8:02pm

Hi guys,

Recently, I have focused on the design of a 10-GHz frequency divider.

I have a question about its operating range.

Why it has a maximum operating frequency? (Due to RC delay?Am I right?)

Why it has a MINIMUN operating frequency? I cannot understand why divider can't work at a lower frequency. :'(

Thanks in advance

Title: Re: frequency divider operating range
Post by ywguo on Oct 27^th, 2008, 10:49pm

Hi jlee,

I assume you mean a CMOS divider, spicifically it is a CML/SCL divider with resistor load, a divider-by-2.

It reaches the maximum clock rate when the clock period approaches the RC time constant. At that tme, the divider fails.

It has a minimum clock rate because the the circuit will oscillate if the the clock rises/falls slowly.

Please refer to Ullas Singh and Michael Green, Dynamics of High-frequency CMOS Dividers, ISCAS 2002, for the details.

Yawei

Title: Re: frequency divider operating range
Post by jlee on Oct 28^th, 2008, 6:00am

Thank you, ywguo.

It is really a CMOS CML divider.

Regards

Title: Re: frequency divider operating range
Post by zwtang on Nov 4^th, 2008, 4:15pm

Hi jlee,
The problem is similar to the one in digital synchronized circuits. If the clock frequency is high, there will exist setup-up time violations. When the clock frequency is slow, hold-up time is important.
Please check the critical paths of each DFFS in your CML/SCL dividers.
Good Luck!

zwtang