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Design >> Analog Design >> how to reject large noise at power supply
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Message started by hzfeiyun on Oct 29^th, 2008, 3:15am

Title: how to reject large noise at power supply
Post by hzfeiyun on Oct 29^th, 2008, 3:15am

i am doing a regulator design, which requires a stable 1.8V output (max. 200mV ripple) even when power supply having a voltage spike from 6V to 3V then back to 6V with 40ns width and 10MHz repeating frequency.

My problem is how to keep this output when this two stage regulator can not give a fast response due to limited bias current, about 20uA.

and, because it also need work under 1.8V, i did not add complex circuit to improve psrr

:)