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Design Languages >> Verilog-AMS >> verilog code in verilogA
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Message started by manodipan on Oct 29^th, 2008, 4:01am

Title: verilog code in verilogA
Post by manodipan on Oct 29^th, 2008, 4:01am

Hi all,
I have a mixed signal circuit .Now do verilog A support code written using verilog (like @posedge(clk))..if not then which way i can write codes for both environments....
Manodipan

Title: Re: verilog code in verilogA
Post by jbdavid on Oct 29^th, 2008, 10:00am

Verilog-A is the analog subset. It will work in a spectre(or spice) netlist..
or in a verilog netlist.

Verilog-AMS is the mixed signal language. Its a superset of Verilog-A and Verilog, with some extra for dealing with the interface.

you can use the verilog-A model in the verilog netlist..
but you cant use the verilog-ams model in the spectre netlist.

Title: Re: verilog code in verilogA
Post by patrick on Oct 29^th, 2008, 10:38am

I think you need to use the predefined macro, __VAMS_ENABLE__. See page 239 of the VAMS 2.3 LRM at,

http://www.verilog.org/verilog-ams/htmlpages/public-docs/lrm/2.3/VAMS-LRM-2-3.pdf

Verilog-AMS HDL supports a predefined macro to allow modules to be written that work with both IEEE
std 1364-2005 Verilog HDL and Verilog-AMS HDL.The predefined macro is called __VAMS_ENABLE__.
This macro shall always be defined during the parsing of Verilog-AMS source text. Its purpose is to support
the creation of modules which are both legal Verilog and Verilog-AMS. The Verilog-AMS features of such
modules are made visible only when the __VAMS_ENABLE__ macro has previously been defined.
Example:
module not_gate(in, out);
input in;
output out;
reg out;
`ifdef __VAMS_ENABLE__
parameter integer del = 1 from [1:100];
`else
parameter del = 1;
`endif
always @ in
out = #del !in;
endmodule