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Design >> RF Design >> Class-E PA design issue (MOS parasitic capacitance)
https://designers-guide.org/forum/YaBB.pl?num=1225601790

Message started by RF_nicholas on Nov 1^st, 2008, 9:56pm

Title: Class-E PA design issue (MOS parasitic capacitance)
Post by RF_nicholas on Nov 1^st, 2008, 9:56pm

Hi to everyone. I am designing a class-E PA for my engineering diploma. The PA is designed in 0.18um (UMC) in Cadence Virtuoso and I 'm facing the following problem.
In the first image you can see the ideal class-E PA and in the second the PA schematic(as proposed by Sokal). The capacitance C of the first image is equal to C1 + Cd of the second image, where Cd is parasitic capacitance of the NMOS. The problem is that I can't calculate the Cd because I can't find it in the specs of the UMC I am using. (Actually, the specs describe some RF CMOS transistors of the library but using them I can't get the 7mm transistor I want.) I do know that generally in a MOS: Cd=Cja*(a*b)+Cjp*(2a+2b) where a:width diffusion area and b:length diffusion area. What I don't know is the Cja and Cjp capacitance parameters in UMC.
Is there anyone who uses the same technology or has experience in PA design that can help me?
Is there any way that I can measure, with some Cadence analysis, the Cd capacitance on my MOS?